Unitary Vias in Semiconductor Substrates
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Solution Overview
Problem
Existing methods for interconnecting semiconductor dies in multi-die packages are time-consuming and costly, often requiring multiple steps and elevating the temperature of the die, which consumes a significant portion of the thermal budget.
Innovation Solution
A method for forming unitary vias and terminals that allows for concurrent conductive path formation within the via and terminal, using a single-step process without realigning the substrate, and eliminating the need for masks or lithography, utilizing techniques like anisotropic etching and bottom-up deposition to create a homogeneous conductive structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional multi-step processes are used to form vias, conductive material, and bond pads, then reliable electrical connections are achieved, but processing time and manufacturing cost increase significantly
Solution Approach 1:
The patent combines the formation of vias, conductive material deposition, and bond pad creation into a single unitary structure formed by one continuous anisotropic etching process. This merging of multiple discrete manufacturing steps into a single integrated process simultaneously achieves reliable electrical connections while dramatically reducing processing time and manufacturing complexity
Solution Approach 2:
The unitary via structure serves multiple functions simultaneously: it acts as the via hole, the conductive path, and the bond pad all in one structure. This multi-functionality eliminates the need for separate formation steps for each component, resolving the contradiction between reliability and processing efficiency
2Manufacturing precision
If traditional multi-step processes with lithography and masks are used, then precise alignment and structure formation are achieved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts and eliminates the lithography and mask steps from the traditional fabrication process. By using direct anisotropic etching to define the unitary via structure, the method removes complex alignment equipment and multiple patterning steps while maintaining precise structural formation through the self-aligned nature of the etching process
Solution Approach 2:
The patent replaces the mechanical lithography system (masks, aligners, photolithography chemistry) with a direct physical etching process. This substitution eliminates the complex mechanical alignment system while achieving comparable or superior precision through the inherent anisotropy of the etching process
3Reliability
If multiple processing steps are used to form connections between stacked dies, then reliable interconnections are achieved, but thermal budget is significantly consumed
Solution Approach 1:
By merging multiple high-temperature processing steps into a single etching operation, the patent reduces the cumulative thermal exposure. The unitary structure formation requires fewer thermal cycles and lower peak temperatures compared to traditional multi-step processes involving sintering, reflow, and multiple annealing steps
4Reliability
If solder balls or fused bumps are used for die interconnection, then electrical connections are established, but manufacturing cost and processing time increase
Solution Approach 1:
The patent replaces expensive solder balls and complex fused bump structures with a simpler, more cost-effective unitary via structure. The simplified design reduces material costs and eliminates the need for expensive alignment and bonding equipment, making the manufacturing process more economical while maintaining connection reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces processing time and cost by forming a reliable, solder-free conductive structure with enhanced conductivity and structural characteristics, while minimizing thermal impact and simplifying the manufacturing process.
Implementation Method 1
utilizing techniques like anisotropic etching and bottom-up deposition to create a homogeneous conductive structure
Implementation Method 2
utilizing techniques like anisotropic etching and bottom-up deposition to create a homogeneous conductive structure
Data Source
Figure 1~2A
Figure 2B~2C
Figure 2D~2E
AI summary
Semiconductor substrates with unitary vias and via terminals, and associated systems and methods are disclosed. A representative method in accordance with a particular embodiment includes forming a blind via (140) in a semiconductor substrate, applying a protective layer (122) to a sidewall surface of the via, and forming a terminal opening (111) by selectively removing substrate material from an end surface of the via, while protecting from removal substrate material against which the protective coating is applied. The method can further include disposing a conductive material in both the via and the terminal opening to form an electrically conductive terminal that is unitary with conductive material in the via. Substrate material adjacent to the terminal can then be removed to expose the terminal, which can then be connected to a conductive structure external to the substrate.