Universal 2.5D Interface Blocks for Multi-Protocol Die Links
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Solution Overview
Problem
Existing integrated circuit packages with multiple dies are limited by interface blocks that support only specific communications protocols, failing to accommodate a variety of memory dies and other types of daughter dies, thus hindering performance and integration.
Innovation Solution
A multichip package with a universal interface block (UIB) that supports a wide range of communications protocols, including memory interface protocols, featuring a processor subsystem, pattern sequencing logic, and adjustable drive strength transmit buffer circuitry, along with configurable crossbar switches and multiple PLL circuits for frequency and phase alignment, enabling high-bandwidth, low-latency data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a specific communications protocol interface block is used, then optimal performance for that particular configuration is achieved, but the system cannot support a wide variety of different memory dies and daughter dies
Solution Approach 1:
The patent implements a universal interface block (UIB) that can dynamically configure and support multiple different communications protocols including memory interface protocols and non-memory interface protocols. This allows a single interface block to replace multiple protocol-specific blocks, enabling the system to accommodate various memory dies and daughter dies while maintaining optimal performance for each protocol through dynamic configuration.
2Adaptability or versatility
If multiple protocol-specific interface blocks are implemented, then support for various daughter dies is improved, but device complexity increases
Solution Approach 1:
The universal interface block consolidates multiple protocol-specific interface blocks into a single multi-functional unit. The UIB contains configurable logic that can be programmed to implement different communications protocols, thereby reducing the total number of interface blocks required while maintaining support for various daughter dies and memory types.
Solution Approach 2:
The interface block employs dynamic configuration capabilities where the UIB can be reprogrammed or reconfigured at runtime to adapt to different protocol requirements. This dynamic nature allows the same hardware structure to serve multiple protocol functions, reducing static complexity while maintaining versatility.
3Power
If drive strength is fixed, then manufacturing simplicity is maintained, but power-performance optimization is limited
Solution Approach 1:
The transmit buffer circuitry incorporates adjustable drive strength control that allows the drive strength to be dynamically tuned based on the specific communication requirements and channel conditions. This adjustability enables optimal power-performance trade-offs for different operating scenarios while maintaining a relatively simple manufacturing process through standardized circuit designs with configurable parameters.
Data Source
AI summary
A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to a daughter die across one or more channels. Each UIB may also include multiple phase-locked loop circuits for providing different clock signals to different portions of the UIB and a 2× clock phase generation logic. Each UIB may include multiple IO modules, each of which may optionally include its own duty cycle correction circuit. Each IO module may include buffer circuits, each of which may have a de-emphasis control logic for adjusting buffer drive strength.