Universal Clock Recovery Module for NRZ and RZ Demodulation

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Solution Overview

Problem

Optical communication networks face challenges in maintaining signal quality due to degradation during transparent transmissions, requiring adaptable bit rates and costly components for different modulation formats, making it difficult to optimize network performance without significant investment.

Innovation Solution

A method and device that use a common clock recovery module for demodulating both Non-Return-to-Zero (NRZ) and Return-to-Zero (RZ) signals, with additional steps for extracting specific bits from RZ signals, allowing for bit rate adaptation based on signal quality using a common demodulation circuit and software-level processing, and utilizing network management information for determining signal types.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If different clock recovery modules are used for each modulation format and bit rate, then signal demodulation accuracy is improved, but device complexity and investment cost increase

Engineering Contradiction:
Improvesignal demodulation accuracyVSAvoiddevice complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent implements a universal clock recovery module that can handle multiple modulation formats (NRZ and RZ) and multiple bit rates through software configuration. The module uses a single phase-locked loop structure that adapts to different signal types by adjusting its parameters via control signals from the network management layer, eliminating the need for separate hardware modules for each format while maintaining accurate demodulation performance

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The clock recovery module dynamically changes its operating parameters based on the detected modulation format and bit rate. The control unit adjusts the phase detector characteristics, loop filter parameters, and sampling rates according to the signal type, allowing the same hardware to optimize its performance for NRZ at 10 Gb/s, RZ at 10 Gb/s, or other combinations without physical reconfiguration

Inventive Principle:
Principle #35Parameter changes

2Productivity

If adaptable components for different bit rates are used at transmitters and receivers, then network performance optimization is improved, but investment cost increases

Engineering Contradiction:
Improvenetwork performanceVSAvoidinvestment cost
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The receiver incorporates a universal demodulation system with a single clock recovery module that can operate across multiple bit rates and modulation formats. This eliminates the need to deploy different hardware components for 10 Gb/s RZ, 10 Gb/s NRZ, or other rate combinations, allowing network operators to optimize performance by adapting software parameters rather than making costly hardware upgrades

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent uses software-based configuration to create virtual copies of specialized demodulation functions within a universal hardware platform. The control unit loads different parameter sets corresponding to various modulation formats and bit rates, effectively replicating the behavior of multiple specialized modules without requiring multiple physical devices, thereby reducing investment while maintaining full functionality

Inventive Principle:
Principle #26Copying

3Device complexity

If a common clock recovery module is used for both NRZ and RZ signals, then device complexity is reduced, but signal processing accuracy may deteriorate

Engineering Contradiction:
Improvedevice complexityVSAvoidsignal processing accuracy
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The clock recovery module is designed with dynamic reconfiguration capabilities that allow it to adapt its internal parameters based on the input signal characteristics. The control unit continuously monitors the signal type and adjusts the phase detector gain, loop filter coefficients, and sampling timing accordingly, ensuring optimal processing accuracy for both NRZ and RZ formats despite using a single hardware structure

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The control unit acts as an intermediary between the universal clock recovery module and the network management layer. It receives information about the incoming signal format and bit rate, then translates this into appropriate configuration parameters for the phase-locked loop, effectively mediating between the diverse signal types and the unified hardware structure to maintain high processing accuracy across all formats

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentEP2207281B1Signal processing method and apparatus in an optical communication network
Publication Date: 2013.03.20 ALCATEL LUCENT SA
  • EP2207281B1 patent drawingFigure 1~6
  • EP2207281B1 patent drawingFigure 2
  • EP2207281B1 patent drawingFigure 3

AI summary

The method involves transforming a received signal that is modulated according to a non-return-to-zero type or return-to-zero type, into a binary signal by an optical receiver independent of the type of modulation. Bit error rate is analyzed at the level of decoding of forward error correction (FEC) type error corrector. Certain bits of the binary signal specific to return-to-zero modulation type are extracted by an extraction module (27) of the receiver, if the modulation type corresponds to the return-to-zero modulation type. Independent claims are also included for the following: (1) a computer program comprising a set of instructions for processing a signal transmitted by a transmitter to a receiver via an optical communication network (2) a device for processing the signal transmitted by the transmitter to the receiver via the optical communication network.