Universal Detection Device for High Speed Digital Interface Testing
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Solution Overview
Problem
Traditional Automatic Test Equipment (ATE) faces challenges in efficiently testing high-speed digital interfaces of integrated circuits due to ultra-high testing frequencies, complex interface timing and protocols, and diverse interface level modes, resulting in high costs, low testing coverage, and development complexity.
Innovation Solution
A universal detection device and method that integrates a mid-end digital ATE machine with high-speed digital test functions, utilizing a mid-speed test channel board and a high-speed test channel board with an FPGA, to achieve flexible and efficient testing of high-speed digital interfaces while maintaining low costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional high-end ATE machine is used for direct testing, then testing flexibility and test coverage are improved, but testing cost increases significantly
Solution Approach 1:
The testing system is segmented into two independent parts: a mid-end ATE machine for general IO testing and a separate high-speed test channel board for high-speed interface testing. This segmentation allows each component to be optimized for its specific function while maintaining overall system flexibility and reducing cost compared to a single high-end ATE machine.
Solution Approach 2:
The high-speed test channel board is designed with universal functionality to support multiple high-speed interface protocols (MIPI, PCle, USB, HDMI, Serdes, DDR) through a single device. The board includes configurable test channels that can be adapted to different interface types, eliminating the need for multiple specialized testing devices.
2Device complexity
If paired chips are used as receivers or transceivers, then testing complexity is reduced, but testing coverage and efficiency decrease
Solution Approach 1:
The patent introduces a high-speed test channel board as an intermediary device between the mid-end ATE machine and the DUT. This intermediary board handles the high-speed signal generation and reception directly, eliminating the need for paired chips while maintaining simple ATE architecture. The test channel board serves as a dedicated high-speed interface that directly tests the DUT without requiring additional paired chips.
3Adaptability or versatility
If FPGA is used to simulate paired chips, then testing coverage is improved, but development complexity and cost increase
Solution Approach 1:
The patent extracts the high-speed testing functionality from the complex FPGA-based paired chip simulation approach. Instead of using FPGA to simulate entire transceiver systems, the invention extracts only the essential high-speed signal generation and reception capabilities into a dedicated test channel board, simplifying the overall system while maintaining comprehensive testing coverage.
4Ease of manufacture
If mid-speed test channel is used for high-speed interface testing, then testing cost is reduced, but testing accuracy and reliability decrease
Solution Approach 1:
The test channel board incorporates dynamic configuration capabilities that allow it to adapt its operating parameters to match the specific high-speed interface being tested. The board can dynamically adjust timing, signal levels, and protocol parameters to ensure accurate and reliable testing at GHz frequencies, overcoming the limitations of static mid-speed test channels.
Data Source
AI summary
The present disclosure discloses a universal detection device and method for a high speed digital interface of an integrated circuit, including a mid speed digital test channel board and a high speed digital test channel board, wherein the mid speed digital test channel board includes a test processor and a mid speed test channel unit; a high speed test channel board interface is arranged on a mid speed test channel group; the high speed digital test channel board includes a test processor board interface, a field programmable gate array (FPGA) code config generator, a high speed test channel driver FPGA capable of configuring an interface protocol, a high speed test channel unit, and a configurable test data processor; and the test processor board interface is connected to a high speed test channel board interface of the mid speed test channel group. The present disclosure can meet a mid speed test requirement of a general IO and meet testing of high speed interfaces. Both high flexibility of an FPGA scheme and low cost of a mid-end automatic test equipment (ATE) machine can be achieved.