Universal Image Scaler Hardware Architecture

Solution Overview

Problem

Current image processing methods require different hardware for scaling-up and scaling-down images, leading to inefficiencies and increased costs, with varying industry standards complicating the design architecture and user experience.

Innovation Solution

An image processing method and apparatus that utilize a line buffer with at least 2N storage cells, along with first and second variables, to perform scaling-up and scaling-down operations using the same hardware, employing a scaling procedure that involves storing and interpolating pixels to generate new pixels, allowing for efficient image resizing without the need for different hardware.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If different hardware are required to scale-up and scale-down images, then scaling operations can be performed, but hardware compatibility is complicated and design architecture becomes complex

Engineering Contradiction:

Improvehardware compatibilityVSAvoiddesign architecture

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements a universal scaler hardware architecture that can perform both scaling-up and scaling-down operations using the same physical device. The scaler uses a line buffer with at least 2N storage cells and applies different algorithms (first algorithm for scaling-down, second algorithm for scaling-up) based on the operation type, allowing one hardware unit to serve multiple functions and eliminate the need for separate hardware for each operation.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Productivity

If different hardware are required to scale-up and scale-down images, then scaling operations can be performed, but the process becomes less efficient

Engineering Contradiction:

Improveprocessing efficiencyVSAvoidhardware configuration

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent implements a universal scaler hardware architecture that can perform both scaling-up and scaling-down operations using the same physical device. The scaler uses a line buffer with at least 2N storage cells and applies different algorithms (first algorithm for scaling-down, second algorithm for scaling-up) based on the operation type, allowing one hardware unit to serve multiple functions and eliminate the need for separate hardware for each operation.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Manufacturing precision

If a large capacity memory is used to store all image data in advance, then optimized images can be achieved, but costs increase

Engineering Contradiction:

Improveimage qualityVSAvoidmemory capacity

Core Design Contradiction:

Manufacturing precisionVSQuantity of substance

Solution Approach 1:

The patent segments the image processing into line-by-line operations using a line buffer with at least 2N storage cells, rather than loading the entire image into memory. The processor reads and processes one line at a time, generating output line by line, which significantly reduces the memory capacity requirement while maintaining image processing quality through systematic pixel interpolation algorithms.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS8081845B2Method and device for scaling-up or scaling-down images with the same hardware

Publication Date: 2011.12.20 SILICON MOTION INC

AI summary

An image processing device is provided, which scales-up or scales-down images with the same hardware. The device of this invention comprises a line buffer, a first variable, a second variable and a scaler. The scaler practices a scaling-down procedure to scale-down images or scaling-up procedure to scale-up images.