Universal Input Data Controller for RSDS and Mini-LVDS Signal Loading
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Solution Overview
Problem
Conventional drive ICs are unable to accommodate different differential input formats such as RSDS and mini-LVDS, requiring redesign for each signal format, leading to lengthy development processes and redundant circuitry.
Innovation Solution
A semiconductor device with a clock signal supply section, input terminals for differential signals, and a selector that switches between clock signals to accommodate both RSDS and mini-LVDS formats, allowing for efficient loading of signals without increasing circuit scale.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a drive IC is designed to support multiple differential input formats (RSDS and mini-LVDS) by providing separate circuits for each format, then the adaptability to different signal formats is improved, but the device complexity and circuit scale increase
Solution Approach 1:
The patent implements a universal input data controller that can process both RSDS and mini-LVDS differential input formats through a single integrated circuit. The controller uses a selector to choose between different clock signals (first clock signal for RSDS, second clock signal for mini-LVDS) based on the input format, allowing one circuit to perform multiple functions without requiring separate dedicated circuits for each format.
2Adaptability or versatility
If separate circuits are provided for different differential input formats, then the adaptability is improved, but the manufacturing cost increases due to redundant circuitry
Solution Approach 1:
The patent merges the functionality for processing RSDS and mini-LVDS signals into a single input data controller circuit. Instead of manufacturing separate circuits for each format, the design combines both signal processing capabilities in one unified circuit that uses a selector to switch between different clock signals based on the input format being processed.
3Adaptability or versatility
If the clock signal frequency is changed to accommodate different differential input formats, then the adaptability to different signal standards is improved, but the device complexity increases due to the need for clock signal switching
Solution Approach 1:
The patent introduces a selector as an intermediary component that manages the switching between different clock signals. The selector acts as a mediator between the multiple clock signal sources (first clock signal for RSDS, second clock signal for mini-LVDS) and the input data controller, simplifying the control logic by providing a centralized mechanism for clock signal selection based on the input format.
Data Source
AI summary
An input signal is segmented by a first data latch into 2 bit segments according to rising and falling edges of a clock signal clk, and latched. When the input signal is an RSDS signal, 2 sets worth of 2 bit data are latched according to rising and falling edges of a clock signal clkx2, using a first output section, a first data holding section, and a second output section. When the input signal is a mini-LVDS signal, 4 clock cycles worth of data are held according to the rising and falling edges of the clock signal clkx2 using the first data holding section and the second output section. One set's worth of 8 bit data is then latched according to a rising edge of a clock signal clkx4 using the first output section, a third output section, a fourth output section, and a fifth output section.