Universal Logic Memory Cell With Positive-Feedback Silicon Logic
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Solution Overview
Problem
Conventional logic memory technologies face challenges in implementing all basic CMOS logic operations in a single cell, require large numbers of transistors for stable operation, consume high power, and are difficult to commercialize due to non-silicon material processes and low device uniformity, limiting integration and processing speed.
Innovation Solution
A universal logic memory block using a triple-gate silicon device with a positive feedback loop, combining logical operations in a single structure through a CMOS process, enabling binary combinational logical operations and memory functions in a silicon-based feedback memory device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional logic memory technology uses volatile memory devices (SRAM, DRAM), then stable operation is achieved, but a large number of transistors are required which limits area and increases power consumption
Solution Approach 1:
The patent combines multiple logic functions (AND, OR, NOT, NAND, NOR, XOR, XNOR) and memory storage into a single universal logic memory cell structure. This merging eliminates the need for separate transistor circuits for each logic operation, reducing the total transistor count from dozens in conventional SRAM/DRAM to just 6 transistors in the universal cell.
Solution Approach 2:
The universal logic memory cell is designed to perform all basic CMOS logic operations and store values within a single cell structure. By making the cell universal and multi-functional, the patent eliminates the need for multiple specialized circuits, thereby reducing device complexity and power consumption while maintaining stable operation.
2Reliability
If logic memory technology is based on nonvolatile memory devices (ReRAM, MRAM, PCRAM), then memory function is improved, but complex non-silicon processes are required which reduce device uniformity and reliability
Solution Approach 1:
The patent uses uniform silicon-based CMOS transistors throughout the universal logic memory cell structure. All 6 transistors are fabricated using the same standard CMOS process, ensuring homogeneous device characteristics, high uniformity, and ease of manufacturing. This eliminates the need for complex non-silicon materials and processes required by ReRAM, MRAM, and PCRAM technologies.
3Productivity
If conventional logic memory cells are designed for specific logic operations, then logic operation performance is optimized, but integration is reduced as individual circuits and wiring are required for each operation
Solution Approach 1:
The universal logic memory cell is designed to perform all basic CMOS logic operations (AND, OR, NOT, NAND, NOR, XOR, XNOR) within a single cell structure. This universality eliminates the need for separate dedicated circuits for each logic operation, significantly improving integration density while maintaining optimized performance for each logic function through selective activation of transistor networks.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Improves processing speed and integration by fusing logical operation and storage functions, reducing power consumption and maintaining logical operation values without structural changes, enhancing computational efficiency compared to conventional CMOS logic circuits.
Implementation Method 1
a universal logic memory block that implements various combinational logical operations in a single structure by combining the results of logical operations in a plurality of universal logic memory cells using a triple-gate silicon device driven by a positive feedback loop
Data Source
AI summary
The present disclosure relates to a universal logic memory block using a plurality of universal logic memory cells. The universal logic memory block according to one embodiment of the present disclosure may implement various combinational logical operations in a single structure by combining logical operation results from a plurality of universal logic memory cells using triple-gate silicon devices driven by a positive feedback loop.