Universal Memory Cell Nanoparticle Segmentation
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Solution Overview
Problem
Current memory technologies face challenges in achieving a balance between speed, endurance, voltage requirements, and scalability, particularly in nonvolatile memory (NVM) devices, which are limited by high programming voltages, slow write/erase speeds, and limited endurance, while volatile memories like DRAM suffer from volatility and high power consumption for refreshing.
Innovation Solution
The development of a universal memory cell that integrates both DRAM and NVM elements with vertically-stacked charge-trapping zones, utilizing nanoparticles of different sizes and compositions to achieve faster programming speeds, lower voltage requirements, and extended endurance, while allowing independent operation of DRAM and NVM elements for efficient data storage and retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If nonvolatile memory (NVM) is used for data storage, then data retention without power is improved, but programming speed deteriorates
Solution Approach 1:
The memory cell is segmented into multiple charge-trapping zones (first charge-trapping zone and second charge-trapping zone) with different functions. The first zone enables fast programming for volatile memory operation, while the second zone provides long-term data retention for nonvolatile memory operation. This segmentation allows the system to achieve both fast programming speeds and long data retention times by operating different zones for different functions.
2Duration of action of stationary object
If nonvolatile memory (NVM) is used for data storage, then data retention without power is improved, but write/erase cycle endurance deteriorates
Solution Approach 1:
The memory structure is divided into two charge-trapping zones that can be independently programmed and erased. The first charge-trapping zone can be rapidly programmed and erased for volatile memory operations without affecting the second zone, which retains data for long periods. This segmentation protects the endurance of the NVM structure by allowing frequent operations in the first zone without degrading the long-term retention capability of the second zone.
3Duration of action of stationary object
If nonvolatile memory (NVM) is used for data storage, then data retention without power is improved, but voltage requirements deteriorate
Solution Approach 1:
The two charge-trapping zones are programmed at different voltage levels. The first zone can be programmed at lower voltages for fast volatile memory operations, while the second zone is programmed at higher voltages only when long-term nonvolatile storage is required. This segmented approach allows the system to operate at lower voltages for frequent operations while maintaining the capability for high-voltage programming when needed for NVM operation.
4Productivity
If DRAM is used for data storage, then programming speed is improved, but data retention without power deteriorates
Solution Approach 1:
The memory cell merges DRAM and NVM elements into a single integrated structure with two charge-trapping zones. The first zone provides fast programming characteristics of DRAM, while the second zone provides long-term data retention of NVM. By combining these two types of memory elements in one cell, the system achieves both fast programming speeds and long data retention times without requiring separate memory devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables a memory cell that retains data for 10 years without power, supports over 10^13 write/erase cycles, operates at voltages less than four times the power supply voltage, and maintains high programming speed, addressing the limitations of both volatile and nonvolatile memories.
Implementation Method 1
The semiconductor construction includes a first charge-trapping zone including a first plurality of nanoparticles and a second charge-trapping zone including a second plurality of nanoparticles
Data Source
AI summary
Some embodiments include memory cells that contain a dynamic random access memory (DRAM) element and a nonvolatile memory (NVM) element. The DRAM element contains two types of DRAM nanoparticles that differ in work function. The NVM contains two types of NVM nanoparticles that differ in trapping depth. The NVM nanoparticles may be in vertically displaced charge-trapping planes. The memory cell contains a tunnel dielectric, and one of the charge-trapping planes of the NVM may be further from the tunnel dielectric than the other. The NVM charge-trapping plane that is further from the tunnel dielectric may contain larger NVM nanoparticles than the other NVM charge-trapping plane. The DRAM element may contain a single charge-trapping plane that has both types of DRAM nanoparticles therein. The memory cells may be incorporated into electronic systems.