Universal Model-Based Layout Pattern Check for Semiconductor Hot Spot Detection
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Solution Overview
Problem
As semiconductor fabrication technologies progress to smaller feature sizes, scaling down designs often results in hot spots such as pinching, bridging, and metal line thickness variations, which affect device performance, and existing methods for detecting and correcting these issues are not entirely satisfactory.
Innovation Solution
A system and method for detecting and correcting hot spots in semiconductor devices using a universal model-based layout pattern check (LPC) that simulates processing steps, ensuring consistency across different EDA tools and vendors, and allows for the identification and modification of potential hot spots during the design phase to prevent yield loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a universal model-based layout pattern check is implemented to simulate processing steps, then manufacturing precision and consistency across different EDA tools are improved, but device complexity and implementation cost increase
Solution Approach 1:
The patent implements a universal model-based layout pattern check system that can simulate multiple different processing steps (etching, deposition, CMP, annealing, etc.) using a single integrated platform. This universal system accepts layout data from different EDA tools and vendors, applies consistent processing models, and produces comparable results across the entire semiconductor manufacturing workflow, eliminating the need for separate specialized tools for each processing step.
Solution Approach 2:
The patent introduces a universal processing model as an intermediary layer between the layout design and the actual manufacturing process. This model acts as a mediator that translates various EDA tool outputs into a standardized format, simulates the physical processing steps, and provides feedback for design optimization without requiring direct integration with each specific manufacturing tool.
2Productivity
If hot spots are detected and corrected during the design phase using simulation, then productivity and yield are improved, but use of energy and computational resources increase
Solution Approach 1:
The patent performs layout pattern checks and hot spot detection during the design phase, before the actual semiconductor manufacturing process begins. By simulating processing steps and identifying potential defects (hot spots) in advance, the system allows designers to correct issues in the layout data without requiring costly rework during manufacturing, thereby improving yield while managing computational resources efficiently.
Solution Approach 2:
The patent creates virtual copies of the semiconductor layout and processing steps through computer simulation. Instead of physically manufacturing test devices to detect hot spots, the system uses computational models to replicate the manufacturing process and identify potential issues, significantly reducing the need for physical prototypes and associated resource consumption.
3Length of moving object
If feature sizes are scaled down to advance technology, then device performance is improved, but manufacturing precision deteriorates due to hot spots
Solution Approach 1:
The patent applies preliminary anti-action by identifying and correcting hot spots and other manufacturing defects in the layout design before the actual fabrication process. The system simulates processing steps to predict where dimensional control issues will occur at scaled-down feature sizes, and allows designers to modify the layout proactively to prevent these issues, rather than reacting to defects after manufacturing.
Data Source
AI summary
Methods and systems for providing processing parameters in a secure format are disclosed. In one aspect, a method for providing semiconductor fabrication processing parameters to a design facility is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a model from the set of processing parameters; converting the model into a corresponding set of kernels; converting the set of kernels into a corresponding set of matrices; and communicating the set of matrices to the design facility. In another aspect, a method for providing semiconductor fabrication processing parameters is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a processing model from the set of processing parameters; encrypting the processing model into a format for use with a plurality of EDA tools; and communicating the encrypted processing model format to a design facility.