Universal Power Sequencing Circuit for Notebook Computers
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Solution Overview
Problem
The existing power sequencing methods for information handling systems require customization for each change in chipset components, leading to increased costs and time delays due to the need for redesigning power sequence circuits to maintain compliance with predefined power up and power down sequences.
Innovation Solution
A power sequencing system using independently operating switches to control power delivery between input and output power rails, with a time delay circuit and configurable discrete components to adjust timing, and a fast discharge circuit to override the time period and control the decay rate of output power rails.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If manufacturer and chipset specific power sequence circuits are developed with customized discrete components, then power sequencing compliance is maintained, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent implements a universal power sequence circuit design that can accommodate multiple chipset configurations through programmable control logic. The circuit uses a microcontroller or programmable logic device that can be configured via software to generate different power sequencing patterns, eliminating the need for hardware customization for each chipset variant while maintaining compliance with power sequencing requirements.
Solution Approach 2:
The patent employs programmable parameters such as resistors, capacitors, and control logic that can be adjusted through software configuration rather than hardware redesign. This allows the same physical circuit to adapt to different chipset requirements by changing electrical parameters (resistance, capacitance, timing values) through programmable components, thereby reducing device complexity while maintaining power sequencing compliance.
2Reliability
If power sequence circuits are redesigned for each change in chipset components, then power sequencing compliance is maintained, but productivity and time to market decrease
Solution Approach 1:
The patent implements a dynamic power sequence circuit that can be reconfigured through software updates rather than requiring physical redesign. The programmable control logic allows the circuit to adapt to new chipset configurations by loading different sequencing parameters and timing values, enabling rapid response to chipset changes without affecting productivity or time to market.
Solution Approach 2:
The patent uses a standardized, reusable power sequence circuit design that can be copied and deployed across multiple product platforms. The programmable nature of the circuit allows the same hardware design to serve multiple chipset configurations, eliminating the need for repeated redesign cycles and accelerating product introduction while maintaining compliance through software-based parameter adjustment.
3Manufacturing precision
If tens to hundreds of discrete components are selected and customized for power sequencing, then precise power control is achieved, but ease of manufacture decreases
Solution Approach 1:
The patent consolidates multiple discrete components (resistors, capacitors, control logic) into an integrated circuit or system-in-package solution. The programmable power sequence controller integrates timing generation, switching control, and parameter storage in a single device, reducing the component count from tens or hundreds to a manageable few components while maintaining manufacturing precision through integrated circuit design and software control.
Data Source
AI summary
For sequencing of power rails, a plurality of switches, which operate independently of each other, are operable to control delivery of power from an input power rail to an output power rail. The delivery of the power is controlled by a control input. A time delay circuit is operable to delay the control input by a time period. An input discrete component, coupled in series with the delay circuit, is configurable to adjust the time period. A fast discharge circuit is enabled to override the time period on a trailing edge of the output power rail. A discharge circuit that is coupled to the output power rail includes an output discrete component, the component being selectable to control a decay rate of the output power rail.