Universal Semiconductor Package with Configurable Core Ratios
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Solution Overview
Problem
The varying core number ratios between accelerator and CPU cores in different types of computers lead to high costs and low efficiency due to the need for custom manufacturing of dies and packages for each application.
Innovation Solution
A package and set of dies that include a combination of CPU and accelerator cores, along with various memory interfaces such as TCI, HBM, and DDR4, connected via die interfaces like GPIF, allowing for flexible core ratio configurations suitable for all types of computers without individual customization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If dies and packages are manufactured with different core number ratios for every type of computer, then the packages are suitable for specific application requirements, but cost increases and efficiency decreases
Solution Approach 1:
The patent implements a universal die design that can be configured for different computer types through software or hardware switching mechanisms. The die includes multiple CPU cores and accelerator cores that can be dynamically allocated to different functions, allowing a single die design to serve multiple application requirements (general-purpose computing, graphics processing, AI inference, etc.) without requiring custom manufacturing for each application.
Solution Approach 2:
The patent employs dynamic core allocation and configuration mechanisms where the operational state of cores can be changed at runtime. The die can switch between different operational modes (e.g., CPU-only mode, GPU-accelerated mode, hybrid mode) based on workload requirements, enabling adaptability without physical reconfiguration or custom manufacturing.
2Adaptability or versatility
If dies and packages are manufactured with different core number ratios for every type of computer, then the packages are suitable for specific application requirements, but cost increases
Solution Approach 1:
The patent implements a universal die design that can be configured for different computer types through software or hardware switching mechanisms. The die includes multiple CPU cores and accelerator cores that can be dynamically allocated to different functions, allowing a single die design to serve multiple application requirements (general-purpose computing, graphics processing, AI inference, etc.) without requiring custom manufacturing for each application.
Solution Approach 2:
The patent utilizes parameter changes in the operational configuration of the die rather than physical manufacturing changes. By adjusting operational parameters (core activation states, memory allocation, interface configurations), the same physical die can adapt to different application requirements, eliminating the need for costly custom manufacturing runs for each application type.
3Adaptability or versatility
If multiple memory interfaces are included to support different memory types, then compatibility with various memory specifications is improved, but device complexity increases
Solution Approach 1:
The patent introduces memory interface controllers as intermediary components that manage communication between the die and different memory types. These controllers act as adapters that translate between different memory protocols (DDR4, HBM, TCI), allowing the core logic to interact with a standardized interface while supporting multiple memory types through the intermediary controllers.
Solution Approach 2:
The patent segments the memory interface functionality into separate, modular interface controllers, each dedicated to a specific memory type. This segmentation allows each controller to be optimized for its specific memory protocol while sharing common resources (such as memory management units and buffer memory), reducing overall complexity compared to having all interfaces fully integrated and interconnected.
Data Source
AI summary
Provided efficiently and at low cost are: a package for core number ratios appropriate for all types of computers; and dies included in the package.This package includes at least one die provided with: at least one of a first core formed of a CPU core or a latency core and a second core formed of an accelerator core or a throughput core; an external interface; memory interfaces 24 to 26; and a die interface 23 which is connected to another die.The die includes a first type die and a second type die each including both the first core and the second core and the core number ratio between the first core and the second core in the first type die differs from that in the second type die.Moreover, the memory interfaces include an interface conforming to TCI.In addition, the memory interfaces further include an interface conforming to HBM.