Universal Semiconductor Testing Circuit Architecture
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Solution Overview
Problem
Current testing methods for semiconductor devices require multiple separate circuits for various tests, increasing time, cost, and complexity, making it desirable to develop a more efficient testing circuit and method that can perform multiple tests simultaneously.
Innovation Solution
A testing circuit comprising two circuits with capacitors, inductors, and diodes, connected to transistors, which operate in both boost and buck modes to efficiently transfer voltage and perform tests like SSOA, aging, and double pulse tests, reducing the need for multiple separate circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple separate testing circuits are used to perform various tests on semiconductor devices, then the testing can be comprehensive, but the time, cost and complexity of testing increase
Solution Approach 1:
The patent implements a universal testing circuit that can perform multiple different tests (buck circuit test, boost circuit test, aging test, SSOA test) using the same circuit architecture. The circuit includes capacitors C1, C2, inductors L1, L2, and transistors Q1, Q2 that can be configured to perform different testing functions by controlling the switching of transistors and the charging/discharging of capacitors, thereby eliminating the need for multiple separate testing circuits and reducing complexity while maintaining comprehensive testing capability
Solution Approach 2:
The patent merges multiple separate testing circuits into a single integrated circuit that can perform all required tests. By combining the buck circuit, boost circuit, aging test circuit, and SSOA test circuit into one unified structure sharing common components like capacitors C1, C2 and inductors L1, L2, the patent reduces the overall complexity, cost, and space required for testing while maintaining the ability to perform all necessary semiconductor device evaluations
2Reliability
If multiple separate testing circuits are used, then various tests can be performed, but the testing time increases
Solution Approach 1:
The patent combines multiple testing functions into a single circuit that can execute different tests sequentially or in parallel. The unified circuit architecture allows for the buck circuit test, boost circuit test, aging test, and SSOA test to be performed without requiring separate testing setups, thereby reducing the total time needed for comprehensive device evaluation while maintaining all necessary testing capabilities
3Reliability
If multiple separate testing circuits are used, then comprehensive testing is achieved, but the cost increases
Solution Approach 1:
The patent creates a universal testing circuit that can perform multiple different tests (buck circuit test, boost circuit test, aging test, SSOA test) using the same circuit architecture. The circuit includes capacitors C1, C2, inductors L1, L2, and transistors Q1, Q2 that can be configured to perform different testing functions by controlling the switching of transistors and the charging/discharging of capacitors, thereby eliminating the need for multiple separate testing circuits and reducing complexity while maintaining comprehensive testing capability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The circuit allows for efficient performance of boost, buck, aging, and SSOA tests with minimal power loss and reduced power consumption, enhancing testing flexibility and reducing the time, cost, and complexity of semiconductor device testing.
Implementation Method 1
The first circuit is configured to transfer at least a portion of a first voltage across the first capacitor to the second capacitor during a period of the first pulse signal
Implementation Method 2
The second circuit further includes a first inductor and a first diode
Implementation Method 3
The first diode has an anode connected to ground and a cathode connected to the second terminal of the first inductor
Data Source
AI summary
A testing circuit includes a first circuit and a second circuit. The first circuit and second circuit have a first capacitor and a second capacitor. The first circuit is connected to a first transistor. The second circuit is connected to a second transistor. A first inductor has a first terminal connected to an input of the testing circuit and a second terminal connected to a source of the second transistor. A first diode has an anode connected to ground and a cathode connected to the second terminal of the first inductor. The second capacitor has a first terminal connected to a drain of the second transistor and a second terminal connected to ground. The first capacitor has a first terminal connected to the input of the testing circuit and a second terminal connected to ground.