Universal Shifter Circuit for Multi-Width Data Processing
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Solution Overview
Problem
Conventional electronic design automation tools struggle to design shifters that can perform both shift and rotate operations on multiple data types with varying widths, such as 8-16-32-64-80 bits, at high frequencies while minimizing die area, and often result in larger die size and lower frequency operation.
Innovation Solution
A universal shifter design is implemented using a two-stage architecture with multiple levels of multiplexers, capable of performing arithmetic and logical shift operations, and supporting both signed and unsigned data types, which is automatically generated using electronic design automation tools to create a single hardware block that can handle multiple partition types and shift amounts without signal saturation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional EDA tools are used to design shifters for multiple data types, then the shifter can handle various data widths, but the die area increases significantly
Solution Approach 1:
The shifter is designed as a universal circuit block that can handle multiple data types (8-bit, 16-bit, 32-bit, 64-bit, 80-bit) and multiple operations (arithmetic shift, logical shift, rotate) within a single unified architecture, eliminating the need for separate shifter circuits for each data type
Solution Approach 2:
The shifter is divided into two stages: a first stage that performs shift/rotate operations without saturation and a second stage that performs operations with saturation, allowing each stage to be optimized for its specific function while sharing common control logic
2Adaptability or versatility
If conventional shifter designs are implemented, then various shift operations can be performed, but the operating frequency is limited and cannot reach Giga-Hertz range
Solution Approach 1:
The first stage performs preliminary shift/rotate operations without saturation constraints, preparing the data for the second stage. This preliminary action allows the critical path to be shorter and enables higher operating frequencies in the Giga-Hertz range
Solution Approach 2:
The shifter uses dynamic control signals (arithlogic shift control, saturate control, partition type control) that allow the circuit to adapt its behavior based on the input data type and desired operation, optimizing performance for different scenarios
3Reliability
If separate shifter circuits are used for different data types, then each circuit can be optimized, but the overall device complexity increases
Solution Approach 1:
A single universal shifter circuit replaces multiple separate shifter circuits for different data types, reducing overall device complexity while maintaining operation accuracy through unified control logic and standardized processing paths
4Adaptability or versatility
If conventional shifter designs are used, then basic shift operations can be performed, but power consumption is high
Solution Approach 1:
By segmenting the shifter into two stages with specialized functions, the circuit can selectively activate only the necessary components for each operation type, reducing overall power consumption while maintaining full operational functionality
Solution Approach 2:
Each stage is optimized for its specific function (first stage for non-saturated operations, second stage for saturated operations), allowing local optimization of power consumption based on the actual operation being performed
Data Source
AI summary
A single block shifter design performing arithmetic and logical shift operations on input operands of multiple types is disclosed. The shifter design may be configurable and automatically generated to support multiple partition types including at least one of 80-bit, 40-bit, and 20-bit partition type. The shifter may also be configured and automatically generated to perform rotate operations on input operands. The shifter may include two stages where the first stage includes multiple multiplexers performing shift or rotate operations by one or more shift or rotate amounts without saturation, and the second stage includes multiple multiplexers performing operations with saturation. The shifter includes an inversion block to process signed and unsigned input data. A method of automatically generating the shifter design with an electronic design tool is also disclosed.


