Universal Streaming Interface for Real-Time Trace Data Analysis
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Solution Overview
Problem
Modern electronic systems face challenges in identifying failure modes due to contamination, parasitic devices, and limited visibility of internal circuit operations, which increases development time and costs, and existing diagnostic methods are inadequate for real-time monitoring and analysis.
Innovation Solution
An electronic system with a universal streaming and logging interface coupled to an internal data path and a direct memory access (DMA) controller, enabling real-time capture and analysis of trace data to identify failure modes without bandwidth limitations, using a support processor chip for detailed failure analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Difficulty of detecting and measuring
If internal circuits are wired to an input/output driver to add visibility to internal circuitry, then diagnostic capability is improved, but internal circuit delay increases and transition frequency is limited by the output driver bandwidth
Solution Approach 1:
The patent introduces a specialized trace interface circuit as an intermediary between the internal data path and external diagnostic equipment. This trace interface includes a trace data bus that captures internal circuit states without requiring standard I/O drivers, thereby providing diagnostic visibility while avoiding the bandwidth limitations and delays associated with general-purpose output drivers.
Solution Approach 2:
The patent segments the diagnostic function from the main data path by creating a dedicated trace data bus and trace interface circuit. This separation allows the main internal circuits to operate at full speed while the trace interface handles diagnostic data capture independently, eliminating the performance penalty that would result from coupling diagnostics directly to the data path.
2Reliability
If testing and analysis is performed at every opportunity to identify failure modes, then manufacturing reliability is improved, but development time and costs increase
Solution Approach 1:
The patent implements preliminary action by capturing and storing trace data continuously or near-continuously during normal circuit operation, so that when a failure occurs, the diagnostic information is already available. This eliminates the need for time-consuming post-failure setup and measurement, as the trace interface has already recorded the internal circuit states leading up to and including the failure event.
Solution Approach 2:
The trace interface circuit is integrated directly into the device under test, allowing the device to perform self-diagnosis. The internal data path automatically drives the trace data bus, and the trace interface automatically captures and stores the data, eliminating the need for external testing equipment and complex external test setups, thereby reducing both time and cost.
3Difficulty of detecting and measuring
If internal data path is monitored in static states only, then circuit operation visibility is improved for stable conditions, but dynamic circuit operation remains invisible
Solution Approach 1:
The trace interface is designed to continuously capture data from the internal data path during dynamic operation, not just in static states. The trace data bus remains active throughout the entire operational sequence, capturing transient signals and dynamic transitions, thereby providing a complete picture of circuit behavior from start to finish without gaps or limitations to steady-state conditions only.
Data Source
AI summary
A electronic system includes: an integrated circuit including: an internal data path, configured to drive a functional output, a universal streaming and logging interface, coupled to the internal data path, to generate a trace data bus, and a direct memory access (DMA) controller, coupled to the universal streaming and logging interface, to manage the storage of the trace data bus; a support circuit, coupled to the integrated circuit, configured to receive the trace data bus; and a support processor chip, coupled to the support circuit, configured to analyze the trace data bus for identifying a failure mode of the integrated circuit.