Universal Test Chiplet for Heterogeneous Integration
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Solution Overview
Problem
The testing of chiplets in heterogeneous integration systems is complex due to the need for customized testing solutions for each chiplet, limited testing resources, and high integration density, which results in inefficiencies and increased hardware overhead.
Innovation Solution
A universal test chiplet is designed to embed shared test resources, featuring a chiplet test control circuit module, a test data distribution circuit module, a memory test configuration circuit module, and a chiplet test interface circuit module, which enables comprehensive, flexible, and efficient testing by distributing test data and configuring test modes across multiple chiplets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a customized testing solution is added for each chiplet to ensure system stability, then testing reliability is improved, but device complexity and hardware overhead increase significantly
Solution Approach 1:
The patent implements a universal test chiplet that can test multiple types of chiplets (CPU, GPU, NPU, etc.) through a single standardized interface. The test chiplet contains configurable test circuits and data distribution networks that can be programmed to perform different testing functions, eliminating the need for customized test solutions for each chiplet type while maintaining testing reliability.
Solution Approach 2:
The patent merges multiple testing functions into a single integrated test chiplet. Instead of having separate test circuits for each chiplet, the invention combines test data generation, distribution, collection, and analysis functions into one unified test chiplet that serves the entire heterogeneous chiplet system, thereby reducing overall device complexity.
2Measurement precision
If test circuits are added in each chiplet to enable comprehensive testing, then measurement precision is improved, but hardware overhead and manufacturing cost increase
Solution Approach 1:
The patent extracts the testing functionality from individual chiplets and relocates it to a separate universal test chiplet. This extraction allows the tested chiplets to focus on their primary functions while the dedicated test chiplet provides comprehensive testing capabilities, reducing hardware overhead in the functional chiplets while maintaining measurement precision.
Solution Approach 2:
The universal test chiplet contains reconfigurable test circuits that can be programmed to perform different testing operations. Instead of having dedicated test circuits in each chiplet, a single universal test chiplet can be configured to test various chiplet types, significantly reducing the total quantity of test hardware required.
3Productivity
If traditional bus-based test data transmission is used, then device complexity is reduced, but productivity and testing efficiency decrease due to limited transmission speed
Solution Approach 1:
The patent transitions from traditional single-dimensional bus-based test data transmission to a multi-dimensional test data distribution network. The test chiplet includes multiple data distribution channels that can simultaneously transmit test data to multiple chiplets, enabling parallel testing and significantly improving productivity while the modular architecture keeps device complexity manageable.
Solution Approach 2:
The test data transmission path is segmented into multiple independent channels within the test chiplet. Instead of using a single shared bus, the invention divides the data transmission into parallel paths, allowing simultaneous testing of multiple chiplets and improving overall testing efficiency without requiring complex cross-chiplet interconnects.
4Adaptability or versatility
If a standardized test interface is implemented across all chiplets, then adaptability and ease of operation are improved, but manufacturing precision requirements increase due to heterogeneous integration
Solution Approach 1:
The universal test chiplet acts as an intermediary between the test controller and the heterogeneous chiplets. It provides a standardized interface to the external test controller while adapting to different chiplet types through configurable internal circuits. This intermediary approach enables test interface compatibility across heterogeneous chiplets without requiring extremely tight manufacturing precision for direct interfacing.
Data Source
AI summary
A universal test chiplet for testing a plurality of chiplets to be tested is provided. The universal test chiplet includes a chiplet test control circuit module, a test data distribution circuit module, a memory test configuration circuit module, and a chiplet test interface circuit module. The chiplet test control circuit module is configured to provide test data and configure test modes for the chiplets to be tested. The test data distribution circuit module is configured to distribute the test data required by each of the chiplets to be tested from a test data bus. The memory test configuration circuit module is configured to provide test circuits for memories of the chiplets to be tested and automatically generate a test vector. The chiplet test interface circuit module is configured to transmit the test data to the chiplets to be tested in any direction through chiplet test interfaces.