Unneeded Block Prediction in Multi-Level Cache Systems
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Solution Overview
Problem
In computing systems, cache inefficiencies arise from storing unneeded blocks in cache levels, such as the last level cache (LLC) and near memory, which occupy space that could be used for needed items, leading to performance degradation.
Innovation Solution
Implementing a two-level prediction unit that identifies blocks likely to be unneeded in either the LLC or near memory cache, preventing them from being cached, and using a multi-level system memory architecture with near memory as a faster cache and far memory as a slower, more storage-oriented system memory, with DRAM chips acting as a memory side cache for non-volatile memory chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If blocks are cached in the last level cache and near memory, then the storage capacity increases, but the cache efficiency deteriorates due to unneeded blocks occupying space
Solution Approach 1:
The prediction unit performs preliminary analysis before caching blocks to determine whether they will be needed. By predicting future access patterns in advance, the system prevents unneeded blocks from being cached, thereby maintaining high cache efficiency while maximizing storage utilization of the cache resources.
2Quantity of substance
If unneeded blocks are stored in cache, then the cache storage is utilized, but the system performance deteriorates due to space occupation by useless data
Solution Approach 1:
The prediction unit extracts and identifies blocks that are likely to be unneeded before they are cached. By separating out these unneeded blocks in advance, the system prevents them from occupying cache space, ensuring that only useful blocks are stored and thus maintaining high system performance while achieving effective storage utilization.
3Speed
If a multi-level memory architecture is implemented with near memory as cache, then the access speed improves, but the device complexity increases
Solution Approach 1:
The memory system is segmented into multiple levels: last level cache, near memory, and far memory. Each level serves a specific purpose and has optimized characteristics for its function. This segmentation allows the system to achieve high access speeds for frequently accessed data in near memory while maintaining manageable complexity through clear functional boundaries and hierarchical organization.
4Use of energy by moving object
If DRAM chips are used as cache for non-volatile memory chips, then the power consumption reduces, but the manufacturing complexity increases
Solution Approach 1:
DRAM chips and non-volatile memory chips are merged into a unified memory system where DRAM serves as near memory cache and non-volatile memory provides bulk storage. This combination leverages the high-speed, low-power characteristics of DRAM for active data while utilizing the non-volatile memory for persistent storage, achieving reduced overall power consumption while managing manufacturing complexity through standardized integration processes.
Data Source
AI summary
An apparatus is described. The apparatus includes a last level cache and a memory controller to interface to a multi-level system memory. The multi-level system memory has a caching level. The apparatus includes a first prediction unit to predict unneeded blocks in the last level cache. The apparatus includes a second prediction unit to predict unneeded blocks in the caching level of the multi-level system memory.