Detecting Unobservable Latch Cycles to Prevent Redundant Switching
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Solution Overview
Problem
Existing circuit designs face inefficiencies due to unobservable cycles in latches, leading to redundant switching that wastes power and is not detectable by downstream logic, which current technologies fail to address effectively.
Innovation Solution
A system utilizing a processor to detect unobservable cycles in latches, generate coverage events, and track state changes through simulation techniques to identify and prevent redundant switching by modifying the circuit design, thereby optimizing power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If latches are used in circuit design to store state information, then the circuit can maintain memory functionality, but unobservable cycles cause redundant switching that increases power consumption
Solution Approach 1:
The system performs preliminary analysis of latch cycles during the design phase to identify unobservable cycles before manufacturing. By detecting and marking these cycles in advance, the design tool can prepare modifications that prevent redundant switching, thereby reducing power consumption while maintaining latch stability.
Solution Approach 2:
The system modifies circuit parameters by introducing modifications to latches in unobservable cycles. These parameter changes alter the switching behavior of latches to eliminate redundant transitions, directly addressing the power consumption issue while preserving the necessary state storage functionality.
2Loss of energy
If comprehensive latch analysis is performed to detect unobservable cycles, then power consumption can be optimized, but the design complexity and analysis time increase
Solution Approach 1:
The system segments the circuit analysis into distinct components: cycle detection, observability analysis, and modification generation. By dividing the complex analysis task into manageable segments, the tool can efficiently process large circuits without overwhelming computational complexity, enabling comprehensive power optimization.
Solution Approach 2:
The system implements feedback mechanisms where the analysis results are used to automatically generate and apply modifications to the circuit design. This closed-loop approach ensures that the complexity of analysis is justified by automated optimization, reducing manual intervention while achieving power consumption goals.
3Productivity
If unobservable cycles are left undetected, then the design process is simpler and faster, but redundant switching occurs causing unnecessary power waste
Solution Approach 1:
The system performs preliminary detection of unobservable cycles during the design phase rather than during operation. This advance detection allows the tool to identify power-wasting issues before they affect actual circuit performance, enabling optimization without delaying the overall design timeline.
Solution Approach 2:
The design tool provides self-service by automatically analyzing latch cycles and generating modifications without requiring manual intervention. This automation maintains high design productivity while eliminating power consumption issues that would otherwise require extensive manual debugging and optimization.
Data Source
AI summary
An unobservable cycle for at least one latch in a circuit design is detected. The unobservable cycle indicates that the at least one latch is not observable to downstream logic in the circuit design. A coverage event is generated to identify the unobservable cycle for the at least one latch. The coverage event is tracked to detect a state associated with the unobservable cycle and a state change cycle. The state change cycle is determined based on a simulation technique. A redundant switching of the at least one latch based on the state associated with the unobservable cycle and the state change cycle is determined. Furthermore, manufacturing of a circuit based on the circuit design is at least initiated. The circuit design is modified to prevent the redundant switching of the at least one latch.


