Unrounded FMA Forwarding with Parallel Alignment Shift
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Solution Overview
Problem
Existing floating-point unit (FPU) designs for performing binary fused multiply-add operations face latency issues due to the need for delayed alignment shifts until rounded results are available, limiting performance in compute-intensive applications like analytics and location detection.
Innovation Solution
A binary fused multiply-add floating-point unit that receives an unrounded result via an early result feedback path, performs alignment shifts on unrounded exponents and mantissas, and applies rounding corrections in parallel, enabled by a rounding-up signal, allowing unrounded forwarding into all operands and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If alignment shifts are performed after rounding (conventional approach), then rounding precision is maintained, but operation latency increases
Solution Approach 1:
The patent performs alignment shifts on unrounded operands before the rounding operation is completed. The aligner receives unrounded inputs and performs shifts in parallel with the rounding process, rather than waiting for rounded results. This preliminary action on unrounded data reduces latency while the rounding correction mechanism ensures precision is maintained.
Solution Approach 2:
The patent implements a feedback mechanism where the rounding result is fed back to correct the alignment shift. The rounded result from the rounder is compared with the shifted unrounded result, and a correction is applied if needed. This feedback loop ensures that the final output maintains proper rounding precision despite the early alignment shift on unrounded data.
2Loss of time
If unrounded results are forwarded early (invention approach), then operation latency is reduced, but rounding precision may be compromised
Solution Approach 1:
The patent introduces a rounding correction mechanism as an intermediary between the early alignment shift on unrounded data and the final rounded output. The correction logic monitors the rounding process and applies adjustments to the shifted result based on the rounding outcome, ensuring that the unrounded forwarding does not compromise final precision.
Solution Approach 2:
The patent replaces the conventional sequential mechanical process (round first, then align) with a parallel process using logical corrections. Instead of physically waiting for rounding to complete before alignment, the system uses logical feedback and correction mechanisms to achieve the same precision outcome while enabling parallel execution and reducing latency.
3Measurement precision
If delayed alignment shifts are performed (conventional approach), then rounding accuracy is ensured, but compute-intensive application performance deteriorates
Solution Approach 1:
The patent performs alignment shifts preliminarily on unrounded operands during the same clock cycle as the multiplication and rounding operations. This preliminary action eliminates the need for delayed shifts in subsequent cycles, thereby improving throughput for compute-intensive applications while maintaining rounding accuracy through the feedback correction mechanism.
Solution Approach 2:
The patent enables continuous useful action by performing alignment shifts in parallel with other FMA operations rather than delaying them. The unrounded forwarding allows the aligner to work continuously without waiting for rounding to complete, improving overall processor productivity while the rounding correction ensures accuracy is maintained.
4Measurement precision
If alignment shifts are performed on rounded results (conventional approach), then precision is maintained, but FPU throughput is limited
Solution Approach 1:
The patent performs alignment shifts preliminarily on unrounded operands before the rounding operation completes. This preliminary action allows the FPU to pipeline multiple operations more efficiently, improving throughput by eliminating sequential dependencies while the rounding correction mechanism preserves precision.
Solution Approach 2:
The patent uses feedback from the rounding operation to correct the preliminary alignment shift on unrounded data. This feedback mechanism allows the FPU to maintain high throughput by performing operations in parallel while ensuring precision is maintained through corrective feedback, thereby resolving the throughput-precision tradeoff.
Data Source
AI summary
A binary fused multiply-add floating-point unit configured to operate on an addend, a multiplier, and a multiplicand. The unit is configured to receive as the addend an unrounded result of a prior operation executed in the unit via an early result feedback path; to perform an alignment shift of the unrounded addend on an unrounded exponent and an unrounded mantissa; as well as perform a rounding correction for the addend in parallel to the actual alignment shift, responsive to a rounding-up signal.