Un-Sampled Decision Feedback Equalizer With Configurable Loop Delay

Solution Overview

Problem

Conventional decision feedback equalizers (DFEs) face challenges such as tight timing constraints, complex structures, and high power consumption, which limit their suitability for high-speed receivers, and often fail to achieve optimal eye openings due to signal reflection and inter-symbol interference.

Innovation Solution

The implementation of an un-sampled DFE structure that eliminates the need for sampled decision components, allowing for a fine fractional loop delay and reducing signal reflection across the eye opening, thereby simplifying the circuit and reducing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional sampled decision circuitry is used in DFE, then decision-making can be performed, but timing constraints become tight and circuit complexity increases

Engineering Contradiction:

Improvedecision accuracyVSAvoidcircuit complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts and removes the sampling clock and sampled decision circuitry from the DFE architecture. By eliminating these components, the invention avoids the timing constraints and complexity associated with conventional sampled decision-making, while still achieving accurate decision through continuous-time processing

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent replaces the mechanical/clock-based sampling system with a continuous-time processing system. Instead of using discrete sampling instants controlled by a clock, the invention processes signals continuously, substituting the mechanical sampling mechanism with a continuous analog computation approach

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Reliability

If conventional sampled decision circuitry is used in DFE, then decision-making can be performed, but power consumption becomes high

Engineering Contradiction:

Improvedecision accuracyVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent extracts and removes the sampling clock and sampled decision circuitry from the DFE architecture. By eliminating these components, the invention avoids the timing constraints and complexity associated with conventional sampled decision-making, while still achieving accurate decision through continuous-time processing

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent replaces the mechanical/clock-based sampling system with a continuous-time processing system. Instead of using discrete sampling instants controlled by a clock, the invention processes signals continuously, substituting the mechanical sampling mechanism with a continuous analog computation approach

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

3Reliability

If conventional DFE structures are used, then equalization can be performed, but signal reflection and inter-symbol interference reduce eye opening quality

Engineering Contradiction:

Improvesignal qualityVSAvoidsignal reflection and inter-symbol interference

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent converts the harmful effects of signal reflection and inter-symbol interference into beneficial feedback signals. By continuously processing the entire signal spectrum and feeding it back through the equalizer, the invention transforms reflections and interference that normally degrade performance into useful information that helps cancel out these harmful effects

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The patent implements continuous feedback of the equalized signal back to the equalizer input. This continuous feedback mechanism allows the equalizer to dynamically adjust and cancel out signal reflections and inter-symbol interference, improving eye opening quality by constantly compensating for these harmful effects

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS10496581B2Un-sampled decision feedback equalizer including configurable loop delay

Publication Date: 2019.12.03 INTEL CORP

AI summary

Some embodiments include apparatus and methods using circuits to receive an input signal, generate an equalized signal, provide the equalized signal to a node, amplify the equalized signal, and generate digital input information from the equalized signal. A delay circuit, including delay elements, is provided to apply a time delay to the digital input information and generate digital output information. A selector in the delay circuit provides feedback information from an output node of one of the delay elements. An adjust circuit, including switches on circuit paths coupled to the node, is provided to control the switches based on the feedback information.