Unsigned Integer Multiply-Accumulate Instruction for Processor Efficiency

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Solution Overview

Problem

Existing add instructions in processor architectures face inefficiencies, particularly in handling carries during large integer multiplication, leading to additional execution slots and clock cycles, which hampers quick data processing.

Innovation Solution

The introduction of unsigned integer multiply-accumulate instructions that optimize processor performance by executing these instructions directly, reducing the need for separate carry handling and enhancing execution efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional add instructions are used for large integer multiplication, then basic addition functionality is provided, but additional execution slots and clock cycles are required to handle carries

Engineering Contradiction:
Improvedata processing speedVSAvoidexecution slots and clock cycles
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent combines multiplication and accumulation operations into a single unified instruction (VMULADD.UW). This merging eliminates the need for separate multiply and add instructions, reducing the total number of execution slots required. The carry handling is integrated into the single instruction execution flow, eliminating additional clock cycles that would be needed for separate carry management operations.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The VMULADD.UW instruction provides multi-functionality by simultaneously performing unsigned integer multiplication, accumulation, and carry handling in one operation. This universal instruction replaces multiple specialized instructions (multiply, add, carry management), improving productivity while reducing the time loss associated with sequential execution of multiple instructions.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If separate carry handling is implemented, then accurate large integer multiplication is achieved, but processor execution efficiency decreases

Engineering Contradiction:
Improvecalculation accuracyVSAvoidexecution efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent merges carry handling into the main multiply-accumulate instruction execution flow. The carry flag is automatically updated as part of the unified VMULADD.UW operation, eliminating separate carry management steps. This ensures calculation accuracy is maintained while significantly improving execution efficiency by removing redundant handling steps.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The VMULADD.UW instruction is self-sufficient in managing carries internally without requiring external intervention or separate instructions. The instruction automatically handles carry generation, propagation, and flag updates as part of its core functionality, maintaining reliability while maximizing productivity through streamlined execution.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS20240168717A1Unsigned integer multiply-accumulate processors, methods, systems, and instructions
Publication Date: 2024.05.23 INTEL CORP
  • US20240168717A1 patent drawing
  • US20240168717A1 patent drawing
  • US20240168717A1 patent drawing

AI summary

A processor of an aspect is to perform operations corresponding to an unsigned integer multiply-accumulate instruction. The unsigned integer multiply-accumulate instruction is to indicate a first unsigned integer, a second unsigned integer, a first register that is have a third unsigned integer, and a second register. The operations include to multiply the first unsigned integer and the second unsigned integer to generate a product and add the product and the third unsigned integer to generate a sum. The operations also include to store a first portion of the sum in the second register. The first portion of the sum includes M least significant bits of the sum. The operations also include to store a second portion of the sum in the first register. The second portion of the sum includes all bits of the sum that are more significant than the M least significant bits. Other processors are also disclosed.