Up/Down Prefetcher for Slow-Moving Stride Pattern Detection

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Solution Overview

Problem

Conventional prefetchers in processing systems often fail to accurately detect 'slow-moving' stride or stream patterns in data accesses, leading to ineffective speculative prefetching due to size limitations and multiple streams operating within a memory page.

Innovation Solution

The implementation of an up/down prefetcher (UDP) that identifies slow-moving patterns by sampling demand cache accesses, incrementing hit counts for adjacent cacheline accesses, and enabling speculative prefetching when thresholds are met, allowing for coordinated prefetching with other prefetchers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If conventional prefetchers use limited access history storage, then device complexity is reduced, but measurement precision of stride/stream patterns deteriorates

Engineering Contradiction:
Improveprefetcher structureVSAvoidstride/stream pattern detection accuracy
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The prefetcher is divided into multiple independent components: a history storage unit for accessing past data, a pattern detection unit for identifying stride/stream patterns, and a prefetch control unit for generating prefetch requests. This segmentation allows each component to be optimized independently, maintaining low overall complexity while improving detection precision through specialized functionality in each segment.

Inventive Principle:
Principle #1Segmentation

2Measurement precision

If conventional prefetchers monitor all data accesses, then measurement precision improves, but use of energy increases

Engineering Contradiction:
Improveaccess pattern detection accuracyVSAvoidprefetcher energy consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The prefetcher implements partial monitoring by selectively tracking only those data accesses that exhibit stride or stream patterns, rather than monitoring all accesses uniformly. The pattern detection unit identifies candidate patterns and the prefetch control unit activates prefetching only for confirmed patterns, performing partial action on the full set of accesses to reduce energy consumption while maintaining detection precision for relevant patterns.

Inventive Principle:
Principle #16Partial or excessive action

3Device complexity

If conventional prefetchers use fixed history size, then device complexity is reduced, but adaptability to different stream patterns deteriorates

Engineering Contradiction:
Improvehistory storage structureVSAvoidmulti-stream pattern handling capability
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The prefetcher implements dynamic history management where the history storage unit can be selectively accessed and updated based on detected stream patterns. When multiple streams are detected, the system dynamically adjusts which history entries are maintained and how they are processed, allowing adaptability to different stream patterns without requiring a fundamentally complex storage structure.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10073785B2Up/down prefetcher
Publication Date: 2018.09.11 ADVANCED MICRO DEVICES INC
  • US10073785B2 patent drawing
  • US10073785B2 patent drawing
  • US10073785B2 patent drawing

AI summary

In a processing system comprising a cache, a method includes monitoring demand cache accesses for a thread to maintain a first running count of a number of times demand cache accesses for the thread are directed to cachelines that are adjacent in a first direction to cachelines that are targets of a set of sampled cache accesses for the thread. In response to determining the first running count has exceeded a first threshold, the method further includes enabling a first prefetching mode in which a received demand cache access for the thread triggers a prefetch request for a cacheline adjacent in the first direction to a cacheline targeted by the received demand cache access.