UPF-Annotated RTL Image Recognition for Low-Power Verification
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Solution Overview
Problem
Existing low power verification tools in electronic design automation (EDA) often flag numerous incorrect violations due to improper unified power format (UPF) constraint settings, leading to tedious debugging and inefficiencies in identifying the root causes of power violations in integrated circuit (IC) designs.
Innovation Solution
Implementing unified power format (UPF) annotated register transfer level (RTL) image recognition to generate combined feature arrays from RTL and UPF settings, using machine learning models to identify and suggest modifications in RTL code and UPF settings to reduce power violations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional low power verification tools are used to check UPF constraint settings, then power violation detection is performed, but numerous incorrect violations are flagged leading to tedious debugging
Solution Approach 1:
The patent introduces an intermediary system that uses machine learning models to analyze the relationship between UPF constraint settings and power violations. This intermediary layer processes the verification data, identifies patterns, and filters out incorrect violations before presenting them to designers, thereby improving detection accuracy and reducing debugging time
Solution Approach 2:
The system implements feedback mechanisms where the results of power violation analysis are fed back into the verification process. The machine learning models learn from previous verification outcomes and UPF setting configurations, continuously improving their ability to distinguish correct from incorrect violations, thus reducing false positives and debugging effort
2Reliability
If UPF constraint settings are manually configured and verified, then power compliance is checked, but the process is tedious and inefficient in identifying root causes
Solution Approach 1:
The patent replaces manual mechanical verification processes with automated machine learning-based analysis. Instead of designers manually configuring and checking UPF constraints, the system uses trained models to automatically analyze power violations, identify root causes, and suggest corrections, thereby maintaining reliability while dramatically improving verification efficiency
Solution Approach 2:
The verification system performs self-service by automatically identifying and flagging incorrect UPF constraint settings without requiring extensive manual intervention. The machine learning models autonomously analyze power violations, trace them to their root causes in the UPF settings, and provide actionable insights, enabling the system to serve itself in the verification process
3Measurement precision
If static verification tools are used to check IC design functionality, then functional violations are identified, but the process requires repeated design changes and re-verification
Solution Approach 1:
The patent applies preliminary action by using machine learning models to predict potential power violations and UPF setting issues before final verification. The system analyzes design patterns and historical data to preemptively identify problems that would require iterative fixing, allowing designers to make informed changes earlier in the design process and reduce verification iterations
Data Source
AI summary
A method is provided. The method includes obtaining, for a particular integrated (IC) design, register transfer level (RTL) code and unified power format (UPF) settings, generating an RTL feature array from the RTL code, arranging features based on a UPF into a UPF feature array, generating, by a processor, a combined feature array for the particular IC design by combining the RTL feature array and the UPF feature array, comparing the combined feature array for the particular IC design with another combined feature array, and reporting differences, based on the comparing, between the combined feature array and the other combined feature array to identify changes in at least one of the RTL code and the UPF settings that resulted in a change in a number of power violations.