Uplink Transport Block Scheduling with Memory Access Limits
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current wireless communication systems face inefficiencies in data transmission due to the limitations in scheduling uplink transport blocks, leading to potential data corruption and inefficient use of air interface resources, particularly when data from multiple logical channels are mapped to a single transmission time interval.
Innovation Solution
A method is introduced where a counter is initialized at the beginning of a packet processing time interval, and data blocks are mapped to transport blocks based on a threshold value, allowing for incremental counter increments and padding or repetition of data within transport blocks to ensure timely memory access and efficient resource utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data from multiple logical channels are mapped to a single transmission time interval, then the productivity of data transmission is improved, but the reliability of data transmission deteriorates due to potential data corruption and memory access conflicts
Solution Approach 1:
The transmission time interval is divided into multiple packet processing time intervals, each with its own counter limit. This segmentation allows data from multiple logical channels to be processed in parallel across different intervals while maintaining reliability within each interval through counter-based memory access control.
Solution Approach 2:
The counter is initialized at the beginning of each packet processing time interval to establish a predetermined memory access limit before data mapping occurs. This preliminary action prevents data corruption by ensuring that memory access constraints are enforced from the start of each processing interval.
2Productivity
If the number of memory access starts is increased to handle more data blocks, then the productivity of data transmission is improved, but the device complexity increases due to additional scheduling control mechanisms
Solution Approach 1:
The counter automatically increments with each memory access start and is initialized at the beginning of each packet processing time interval without requiring complex external control. This self-service mechanism simplifies the scheduling control while enabling efficient handling of multiple data blocks within the counter limit.
Solution Approach 2:
The counter limit parameter is configured to define the maximum number of memory access starts per packet processing time interval. By adjusting this parameter, the system can flexibly control the balance between productivity and complexity without changing the underlying scheduling architecture.
3Productivity
If packet processing time interval duration is extended to allow more memory access operations, then the productivity is improved, but the loss of time for each individual data block processing increases
Solution Approach 1:
The system uses periodic packet processing time intervals with initialized counters to create regular processing cycles. This periodic structure allows multiple data blocks to be processed efficiently within each interval while maintaining predictable timing characteristics and preventing excessive delays for individual blocks.
Solution Approach 2:
By dividing the transmission time interval into multiple packet processing time intervals, the system processes data in smaller, more frequent segments. This reduces the processing delay for individual data blocks while maintaining high overall throughput through parallel processing across intervals.
Data Source
AI summary
Certain aspects of the present disclosure relate to wireless communications, and more particularly, to techniques for preparing data for transmission from a user equipment in a wireless communication system. In some embodiments, a method may limit memory access starts during a time interval to ensure that all memory access operations are completed with a transmission time interval.