Upper Conductive Patterns in Semiconductor Packages
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Solution Overview
Problem
Semiconductor packages face challenges in miniaturization and cost reduction due to the increasing integration of semiconductor chips, requiring innovative solutions for reducing size and manufacturing costs while maintaining electrical connectivity.
Innovation Solution
A semiconductor package design featuring a lower redistribution structure with a wiring layer, via connections, a connection substrate with conductive patterns, and an upper redistribution structure that includes a redistribution via connected to a second upper conductive pattern, allowing for reduced package size and simplified manufacturing by eliminating the need for deep holes in the encapsulant.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the semiconductor chip size is reduced for miniaturization, then the package size can be reduced, but the board mounting options become limited
Solution Approach 1:
The patent introduces upper conductive patterns (first and second upper conductive patterns) disposed at different heights above the base layer, creating a three-dimensional conductive structure. This vertical dimensionality allows the package to maintain electrical connectivity and mounting versatility while reducing the horizontal footprint and overall package size.
Solution Approach 2:
The patent embeds the semiconductor chip within a cavity formed in the connection substrate, surrounded by encapsulant material. This nesting approach allows the chip to be integrated within the substrate structure rather than mounted on the surface, reducing the overall package volume while maintaining electrical connections through the substrate.
2Reliability
If deep holes are created in the encapsulant for redistribution vias, then electrical connectivity can be achieved, but the manufacturing complexity and cost increase
Solution Approach 1:
The patent forms the upper conductive patterns on the base layer before the encapsulant is fully cured or before final package assembly. This preliminary action allows the conductive structures to be pre-positioned and integrated into the substrate, eliminating the need for subsequent deep hole drilling and via formation through the cured encapsulant, thereby simplifying manufacturing.
Solution Approach 2:
The patent extracts the redistribution function from the encapsulant material and relocates it to the connection substrate structure. By forming conductive patterns directly on the base layer and using the substrate itself as the redistribution medium, the design eliminates the need for complex via structures through the encapsulant, reducing manufacturing steps and costs.
Data Source
AI summary
A semiconductor package includes a lower redistribution structure including a wiring layer, and a via connected to the wiring layer, a connection substrate on the lower redistribution structure, the connection substrate including a base layer, lower conductive patterns in the base layer, first upper conductive patterns disposed on the base layer, the first upper conductive patterns including an upper pad, and a second upper conductive pattern disposed on the upper pad, a semiconductor chip disposed on the lower redistribution structure and disposed in a cavity of the connection substrate, an encapsulant covering the lower redistribution structure, the connection substrate and the semiconductor chip, and an upper redistribution structure on the encapsulant. The upper redistribution structure includes a redistribution via connected to the second upper conductive pattern.