Upper Contact Plug Structure for Dense Semiconductor Wiring
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Solution Overview
Problem
The demand for high integration and miniaturization of semiconductor devices requires advanced technologies for reducing the size of semiconductor memory devices, particularly in the disposition of wirings within narrow spaces, which existing technologies have not adequately addressed.
Innovation Solution
The semiconductor device incorporates an upper wiring layer and upper contact plugs that extend through a wiring insulating layer, connecting to both lower and upper wiring layers, enabling efficient electrical connectivity and reducing device size while maintaining structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If existing wiring technologies are used in narrow spaces, then device size can be maintained, but integration density and miniaturization are insufficient
Solution Approach 1:
The patent implements upper wiring layers positioned above lower wiring layers in a vertical stacking configuration, transitioning from planar two-dimensional wiring to three-dimensional spatial arrangement. This dimensional change enables higher integration density within a reduced footprint area, directly addressing the contradiction between increasing integration and reducing device size.
Solution Approach 2:
The patent employs a nested structure where upper wiring layers are positioned above and connected to lower wiring layers through contact plugs that extend through insulating layers. This nesting approach allows multiple wiring levels to be compactly arranged vertically, achieving high integration density while minimizing the horizontal device footprint.
2Adaptability or versatility
If upper wiring layers and contact plugs are added to enhance connectivity, then integration and performance improve, but device complexity increases
Solution Approach 1:
The patent divides the wiring system into distinct segments: lower wiring layers, upper wiring layers, wiring insulating layers, and contact plugs. Each segment performs a specific function and can be independently designed and manufactured. This segmentation enables flexible configuration of wiring connections while maintaining manageable structural complexity through modular design.
Solution Approach 2:
The patent introduces wiring insulating layers as intermediary elements between lower and upper wiring layers. These insulating layers provide electrical isolation while allowing contact plugs to pass through and establish connections. The intermediary structure enables complex multi-layer wiring connectivity while maintaining clear structural boundaries that simplify manufacturing processes.
Data Source
AI summary
A semiconductor device includes a substrate including a cell area having a first active region and a peripheral circuit area having a second active region, a direct contact contacting the first active region in the cell area, a bit line structure disposed on the direct contact, a capacitor structure electrically connected to the first active region, a gate structure disposed on the second active region in the peripheral circuit area, lower wiring layers disposed adjacent to the gate structure and electrically connected to the second active region, upper wiring layers disposed on the lower wiring layers, a wiring insulating layer disposed between the lower wiring layers and the upper wiring layers, and upper contact plugs connected to at least one of the lower wiring layers and the upper wiring layers and extending through the wiring insulating layer.