Upper Electrode Topology for MRAM Via Electromigration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The concentration of current through via contacts in semiconductor memory devices, such as MRAMs, leads to electromigration issues that reduce the reliability of the devices due to metal material deterioration.
Innovation Solution
The design includes upper electrodes that are commonly connected to multiple magnetic tunnel junction elements, extending along the second bit lines and shared via contacts, dispersing the write current and reducing the resistance between the electrodes and bit lines, thereby preventing current concentration and electromigration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple selection transistors are provided to cause sufficient write current through MTJ elements, then the write capability is improved, but the current concentration on via contacts increases causing electromigration
Solution Approach 1:
The via contact connection structure is segmented from a single concentrated connection to multiple distributed connections. Each upper electrode is connected to the second bit line through multiple via contacts arranged in series along the bit line, distributing the current path and reducing current density at each individual via contact interface.
Solution Approach 2:
The connection topology is changed from a point-to-point connection to a distributed linear arrangement. The via contacts are arranged in series along the second bit line, extending the connection in the spatial dimension and distributing the current load across multiple locations rather than concentrating it at a single point.
2Productivity
If upper electrodes are commonly connected to multiple MTJ elements, then integration density is improved, but current concentration on via contacts increases
Solution Approach 1:
The via contact connection is segmented into multiple series-connected contacts along the second bit line. This segmentation distributes the current from multiple MTJ elements across multiple via contact interfaces, preventing current concentration while maintaining the shared electrode structure for high integration density.
Solution Approach 2:
The second bit line serves as an intermediary conductor between the commonly shared upper electrode and the MTJ elements. The series arrangement of via contacts along this intermediary path distributes the current flow, allowing multiple MTJ elements to share the electrode without concentrating current at a single via contact point.
3Device complexity
If via contacts are used to connect upper electrodes to second bit lines, then device complexity is reduced, but electromigration occurs due to current concentration
Solution Approach 1:
The simple via contact structure is enhanced by segmenting it into multiple series-connected via contacts. This maintains the basic via contact technology and process simplicity while distributing the current load across multiple contacts, preventing electromigration without significantly increasing device complexity.
Solution Approach 2:
The configuration parameter of the via contact connection is changed from a single contact to multiple series contacts. This parameter change in the connection topology distributes the current density while maintaining the via contact fabrication process and overall structural simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses electromigration in the via contacts, enhancing the reliability and integration density of the semiconductor memory devices while maintaining low power consumption and production costs.
Implementation Method 1
magnetic tunnel junction elements arranged on a semiconductor substrate
Implementation Method 2
A plurality of upper electrodes are respectively connected to second ends of the plurality of magnetic tunnel junction elements
Implementation Method 3
A plurality of selection transistors are electrically connected to first ends of the plurality of magnetic tunnel junction elements
Data Source
AI summary
A semiconductor memory device according to an embodiment includes: a plurality of magnetic tunnel junction elements arranged on a semiconductor substrate; and a plurality of selection transistors electrically connected to first ends of the plurality of magnetic tunnel junction elements. A plurality of first bit lines are respectively connected to the first ends of the magnetic tunnel junction elements via one or more of the selection transistors. A plurality of upper electrodes are respectively connected to second ends of the plurality of magnetic tunnel junction elements. A plurality of second bit lines are respectively connected to the second ends of the magnetic tunnel junction elements via the upper electrodes. The upper electrodes extend along the second bit lines, and one of the upper electrodes is commonly connected to the second ends of the plurality of magnetic tunnel junction elements arranged in an extending direction of the second bit lines.