Upper Gate Contact Structure for 3D Memory Integration
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Solution Overview
Problem
The existing semiconductor devices face limitations in terms of integration density and productivity, particularly in three-dimensional non-volatile memory devices, where the process of forming gate contact portions is complex and time-consuming.
Innovation Solution
A semiconductor device is designed with a substrate that includes a circuit region and a cell region, where the cell region features a gate stacking structure, channel structures, through-gate contact portions, and upper gate contact portions. The upper gate contact portion is formed in a way that it includes multiple portions with different lengths and widths, allowing for a simplified process step by omitting the separate formation of gate contact portions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate process step is used to form gate contact portions in existing semiconductor devices, then the gate contact portions can be formed, but the manufacturing process becomes complex and time-consuming, reducing productivity
Solution Approach 1:
The patent merges the formation of the upper gate contact portion with the formation of the insulation pattern into a single integrated process step. The upper gate contact portion is formed as an integrated part of the insulation pattern structure, eliminating the need for separate process steps to form gate contact portions, thereby simplifying the manufacturing process and improving productivity while maintaining reliable gate contact formation
2Reliability
If the upper gate contact portion is formed with multiple portions of different lengths and widths, then the distribution and stability of contact portions are improved, but the structural complexity increases
Solution Approach 1:
The upper gate contact portion is segmented into multiple portions with different lengths and widths that are integrated within the insulation pattern structure. This segmentation allows different regions of the contact portion to serve specific functions for improved distribution and stability, while the integration within the existing insulation pattern minimizes the increase in overall structural complexity
3Quantity of substance
If the degree of integration of memory devices is increased to improve storage capacity, then more memory cells can be stored, but the manufacturing process becomes more complex and difficult to control
Solution Approach 1:
The insulation pattern structure is designed to serve multiple functions simultaneously: it provides electrical insulation, forms the upper gate contact portion, and enables connectivity between different regions (cell array and circuit region). This multi-functionality allows for increased integration and storage capacity while avoiding the need for additional separate structures, thereby controlling the complexity of the manufacturing process
Data Source
AI summary
A semiconductor device includes a substrate including a circuit region and a cell region. The cell region includes a gate stacking structure, a channel structure that extends into the gate stacking structure and is on the cell array region, a through-gate contact portion that extends into the gate stacking structure and is electrically connected to a connection gate electrode, and an upper gate contact portion that is electrically connected to an upper gate electrode, where the upper gate electrode is separated from the substrate by a first distance, the connection gate electrode is separated from the substrate by a second distance, and where the second distance is less than the first distance, and where the upper gate contact portion includes a first portion and a second portion, and a boundary between the first portion and the second portion has a step shape.