Upper Wiring Structure With Hydrogen Oxide Layer for Lower Thermal Resistance
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Solution Overview
Problem
As semiconductor devices become more integrated, the height of the upper wiring structure increases, leading to elevated vertical thermal resistance due to the stacking of wirings, which affects the device's performance.
Innovation Solution
The semiconductor device incorporates a specific structure with lower metal wirings, multiple insulating interlayers, and an oxide layer for hydrogen supply, where the uppermost via's thickness is less than 40% of the uppermost metal pattern's thickness, reducing the overall thickness and thermal resistance of the upper wiring structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the height of the upper wiring structure is increased to accommodate more stacked wirings for high integration, then the integration level is improved, but the vertical thermal resistance increases
Solution Approach 1:
The patent changes the thickness parameter of the uppermost via to be less than 40% of the uppermost metal pattern thickness, which optimizes the thermal conduction path and reduces vertical thermal resistance while maintaining high integration through multiple stacked wirings
Solution Approach 2:
The patent employs an oxide layer for supplying hydrogen in combination with multiple insulating interlayers and metal wirings, creating a composite structure that manages thermal properties and reduces vertical thermal resistance in the highly integrated wiring structure
2Temperature
If the thickness of the uppermost via is reduced to less than 40% of the uppermost metal pattern thickness, then the vertical thermal resistance is decreased, but the manufacturing precision requirement increases
Solution Approach 1:
The patent specifies a precise parameter range for the uppermost via thickness (less than 40% of the uppermost metal pattern thickness), which optimizes thermal resistance while providing a clear manufacturing target that balances precision requirements with performance benefits
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration decreases the vertical thermal resistance and improves electrical characteristics by reducing the thickness of the uppermost wiring and supplying hydrogen to eliminate dangling bonds, enhancing data retention and refresh operation efficiency in memory devices.
Implementation Method 1
an oxide layer for supplying hydrogen on the second upper insulating interlayer. The oxide layer for supplying hydrogen covers the uppermost wiring
Data Source
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AI summary
A semiconductor device may include lower metal wirings (154, 166, 176, 186, 196) on a substrate (100), a first upper insulating interlayer (200) on the lower metal wirings (154, 166, 176, 186, 196), a first upper wiring (208) including a first upper via (202) in the first upper insulating interlayer (200) and a first upper metal pattern (204) on the first upper insulating interlayer (200). The semiconductor device includes a second upper insulating interlayer (210) on the first upper insulating interlayer (200), an uppermost wiring (218) including an uppermost via (212) in the second upper insulating interlayer (210), an uppermost metal pattern (214) on the second upper insulating interlayer (210), and an oxide layer (220) for supplying hydrogen on the second upper insulating interlayer (210). The lower metal wirings (154, 166, 176, 186, 196) are stacked in a plurality of layers. The oxide layer (120) for supplying hydrogen covers the uppermost wiring (218). A thickness of the uppermost via (202) may be less than 40% of a thickness of the uppermost metal pattern (214).