Uppermost Wiring Structure for Lower Thermal Resistance in Semiconductors
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Solution Overview
Problem
As semiconductor devices become more integrated, the height of the upper wiring structure increases, leading to elevated vertical thermal resistance, which affects the device's performance and efficiency.
Innovation Solution
The semiconductor device incorporates a layered structure with a thin uppermost via and metal pattern, where the via's thickness is less than 40% of the metal pattern's thickness, and an oxide layer for hydrogen supply to reduce thermal resistance and improve electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the upper wiring structure height is increased to accommodate higher integration, then the device can support more circuit layers, but the vertical thermal resistance increases
Solution Approach 1:
The patent applies local quality by creating an asymmetric via structure where the uppermost via has a reduced thickness (less than 40% of the uppermost metal pattern thickness) compared to other vias. This localized modification at the uppermost wiring layer reduces thermal resistance in the critical upper region while preserving the overall high integration structure with multiple stacked metal layers.
Solution Approach 2:
The patent changes the dimensional parameter of the uppermost via thickness to be less than 40% of the uppermost metal pattern thickness, which is a significant deviation from conventional via dimensions. This parameter change directly addresses the thermal resistance issue by creating a lower thermal barrier at the uppermost layer, facilitating better heat dissipation while maintaining the high integration architecture.
2Productivity
If the upper wiring structure height is increased for higher integration, then more circuit layers can be accommodated, but heat dissipation becomes more difficult
Solution Approach 1:
The patent applies local quality by creating an asymmetric via structure where the uppermost via has a reduced thickness (less than 40% of the uppermost metal pattern thickness) compared to other vias. This localized modification at the uppermost wiring layer reduces thermal resistance in the critical upper region while preserving the overall high integration structure with multiple stacked metal layers.
Solution Approach 2:
The patent changes the dimensional parameter of the uppermost via thickness to be less than 40% of the uppermost metal pattern thickness, which is a significant deviation from conventional via dimensions. This parameter change directly addresses the thermal resistance issue by creating a lower thermal barrier at the uppermost layer, facilitating better heat dissipation while maintaining the high integration architecture.
3Ease of manufacture
If conventional via dimensions are used in highly integrated devices, then manufacturing is simpler, but leakage currents increase
Solution Approach 1:
The patent applies local quality by creating an asymmetric via structure where the uppermost via has a reduced thickness (less than 40% of the uppermost metal pattern thickness) compared to other vias. This localized modification at the uppermost wiring layer reduces thermal resistance in the critical upper region while preserving the overall high integration structure with multiple stacked metal layers.
Solution Approach 2:
The patent changes the dimensional parameter of the uppermost via thickness to be less than 40% of the uppermost metal pattern thickness, which is a significant deviation from conventional via dimensions. This parameter change directly addresses the thermal resistance issue by creating a lower thermal barrier at the uppermost layer, facilitating better heat dissipation while maintaining the high integration architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration decreases the thickness of the uppermost wiring, thereby reducing vertical thermal resistance and enhancing the semiconductor device's electrical performance by minimizing leakage currents and increasing data retention time.
Implementation Method 1
an oxide layer for supplying hydrogen on the second upper insulating interlayer
Data Source
AI summary
A semiconductor device may include lower metal wirings on a substrate, a first upper insulating interlayer on the lower metal wirings, a first upper wiring including a first upper via in the first upper insulating interlayer and a first upper metal pattern on the first upper insulating interlayer. The semiconductor device may also include a second upper insulating interlayer on the first upper insulating interlayer, an uppermost wiring including an uppermost via in the second upper insulating interlayer, an uppermost metal pattern on the second upper insulating interlayer, and an oxide layer for supplying hydrogen on the second upper insulating interlayer. The lower metal wirings may be stacked in a plurality of layers. The oxide layer for supplying hydrogen may cover the uppermost wiring. A thickness of the uppermost via may be less than 40% of a thickness of the uppermost metal pattern.