Upright Half-Bridge Semiconductor Package for Smaller Footprint
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Solution Overview
Problem
Semiconductor packages occupy a larger area on circuit boards, limiting space efficiency and requiring larger chips to reduce resistance, which complicates thermal management and increases package parasitics.
Innovation Solution
A semiconductor package with a half-bridge circuit comprising two transistor devices arranged vertically, where the first and second transistor devices are mounted on leads with L-shaped configurations, allowing for upright mounting and reducing the package's footprint by utilizing the chip thickness and width rather than length, enabling double-sided cooling and reduced parasitics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If transistor devices are arranged horizontally in a semiconductor package, then the package occupies a larger area on the circuit board, but the chip length can be used for resistance reduction
Solution Approach 1:
The patent transitions from horizontal arrangement to vertical arrangement of transistor devices within the package. The first and second transistor devices are positioned one above the other in the vertical direction, with their active surfaces facing opposite directions. This dimensional change reduces the package footprint area on the circuit board while maintaining effective current paths through the vertical stacking of device layers and interconnect structures.
Solution Approach 2:
The patent implements nested positioning where the first transistor device is vertically positioned above the second transistor device within the same package footprint. The devices are arranged in a stacked configuration where one device is contained within the vertical space above the other, maximizing space utilization. The leads and interconnect structures are also nested to provide electrical connections between the stacked devices while maintaining compact dimensions.
2Area of stationary object
If transistor devices are arranged vertically, then the package footprint is reduced and thermal performance improves, but the manufacturing complexity increases
Solution Approach 1:
The patent divides the package into distinct vertical segments: a first lead region containing the first transistor device, and a second lead region containing the second transistor device. The leads are segmented into first and second portions that extend in opposite directions to connect to respective transistor devices. This segmentation simplifies the manufacturing process by allowing independent positioning and connection of each device segment while maintaining the compact vertical footprint.
Solution Approach 2:
The patent employs asymmetric positioning where the first and second transistor devices are oriented with their active surfaces facing opposite directions (first device faces upward, second device faces downward). The leads are also asymmetrically configured with first and second portions extending in opposite directions. This asymmetric arrangement optimizes thermal pathways and electrical connections while maintaining manufacturing feasibility through standardized asymmetric bonding processes.
3Reliability
If larger chips are used to reduce resistance, then the electrical performance improves, but the package area and thermal management complexity increase
Solution Approach 1:
The patent reduces resistance by extending current paths in the vertical dimension rather than requiring larger horizontal chip areas. Multiple transistor devices are stacked vertically with interconnect structures providing low-resistance pathways through the vertical stack. This approach maintains small package footprint while achieving low resistance through increased vertical conductivity paths and optimized lead configurations.
Solution Approach 2:
The patent combines multiple transistor devices and their interconnect structures into a single integrated vertical package. The first and second transistor devices are electrically connected through shared lead structures and interconnect layers, creating a unified low-resistance electrical pathway. This merging of multiple components into a compact vertical assembly reduces overall resistance while maintaining a small package area compared to horizontal arrangements.
Data Source
AI summary
A semiconductor package includes low voltage and high voltage contact pads, an output contact pad, a half-bridge circuit, and first, second and third leads. The half bridge circuit includes first and second transistor devices coupled in series at an output node. Both transistor devices have a first major surface which extends substantially perpendicularly to the low voltage contact pad, the high voltage contact pad, and the output contact pad. Both transistor devices are arranged in a device portion of the package and are mounted on a first lead, the first lead providing the output contact pad and being arranged on a first side of the device portion. The second and third leads are arranged in a common plane on a second side of the device portion that opposes the first side. The second lead provides the low voltage pad and the third second lead provides the high voltage output pad.