Upright Half-Bridge Semiconductor Package for Smaller PCB Footprint
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Solution Overview
Problem
Conventional semiconductor packages occupy more space on circuit boards due to their horizontal arrangement, limiting density and requiring larger areas for higher-dimensional chips, which hampers electrical and thermal performance.
Innovation Solution
A semiconductor package with a vertical arrangement of transistor devices and leads, featuring a half-bridge circuit with transistors mounted perpendicularly to the contact pads, allowing for upright mounting and reducing the package's footprint by utilizing a stacked configuration with leads extending perpendicularly to the mounting surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If transistor devices are arranged horizontally in conventional semiconductor packages, then the package structure is simple and easy to manufacture, but the package occupies more space on circuit boards
Solution Approach 1:
The patent transitions from a conventional horizontal arrangement of transistor devices to a vertical arrangement where the first and second transistor devices are positioned one above the other. This dimensional change from 2D horizontal layout to 3D vertical stacking significantly reduces the package footprint on the circuit board while maintaining all necessary electrical connections and functionality
2Quantity of substance
If larger chips are used to accommodate higher-dimensional requirements, then device functionality is improved, but the area occupied on the circuit board increases
Solution Approach 1:
The patent enables the use of larger chips by stacking them vertically in the Z-direction rather than expanding them horizontally in the X-Y plane. The first and second transistor devices can be larger in area while occupying the same or reduced footprint on the circuit board because their increased size is accommodated through vertical stacking with intermediate connection structures
3Reliability
If conventional horizontal mounting is used, then manufacturing and assembly are straightforward, but thermal management and electrical performance are limited
Solution Approach 1:
The vertical arrangement of transistor devices with intermediate connection structures enables improved thermal management by providing multiple pathways for heat dissipation in the vertical direction. Electrical performance is enhanced through reduced parasitic inductance and optimized current paths, while the intermediate connection structures maintain manufacturing feasibility through standardized bonding processes
Data Source
Figure 1A~1D
Figure 1E~1F
Figure 1G
AI summary
In an embodiment, a semiconductor package comprises a low voltage contact pad, a high voltage contact pad, an output contact pad, a half-bridge circuit and a first, a second and a third lead. The half bridge circuit comprises a first transistor device and a second transistor device coupled in series at an output node. The first transistor device has a first major surface and the second transistor device has a first major surface and the first major surface of the first transistor device and of the second transistor device extends substantially perpendicularly to the low voltage contact pad, the high voltage contact pad and the output contact pad. The first and second transistor devices are arranged in a device portion of the semiconductor package and are mounted on a first lead, the first lead providing the output contact pad and being arranged on a first side of the device portion. The second and third leads are arranged in a common plane on a second side of the device portion that opposes the first side. The second lead provides the low voltage pad and the third second lead provides the high voltage output pad.