Upturned Mirror Interposer for Wafer-Level PIC Optical Testing
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Solution Overview
Problem
Existing methods for accessing optical signals in photonic integrated circuits (PICs) during fabrication are limited, hindering effective wafer-level testing and increasing processing costs.
Innovation Solution
The development of an upturned mirror structure on an interposer substrate allows for optical signal access and testing through the use of a probe head with both electrical and optical portions, enabling wafer-level evaluation of PIC performance by reflecting signals perpendicularly to the substrate surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If traditional methods are used to access optical signals in PICs during fabrication, then the existing structure can be maintained, but access to optical signals is limited and wafer-level testing is hindered
Solution Approach 1:
The patent introduces upturned mirrors that reflect optical signals from the planar waveguide layer upward through the substrate to the top surface, enabling access from a different spatial dimension. This allows probe heads to access optical signals during wafer-level fabrication without requiring complex modifications to the waveguide structure itself.
Solution Approach 2:
The upturned mirrors act as intermediary elements that facilitate the transfer of optical signals from the buried planar waveguides to the external probe head. The mirrors provide a coupling mechanism that enables non-contact optical access while maintaining the integrity of the underlying waveguide structure.
2Productivity
If wafer-level testing is implemented with upturned mirrors, then processing costs are reduced and testing efficiency is improved, but the structure becomes more complex
Solution Approach 1:
The testing function is segmented into separate upturned mirror structures that can be independently formed in the interposer layer. This allows multiple test points to be created across the wafer surface without requiring complex integrated testing circuits, enabling parallel testing of multiple PIC devices simultaneously.
Solution Approach 2:
The upturned mirrors are formed in the interposer structure before the final PIC assembly is completed. This preliminary formation of testing infrastructure allows wafer-level testing to be performed during fabrication, enabling early detection of defects and reducing the need for costly post-fabrication testing.
3Ease of manufacture
If direct optical access is enabled through upturned mirrors, then wafer-level testing is facilitated, but the mirror formation process adds complexity to fabrication
Solution Approach 1:
The upturned mirrors are formed using standard semiconductor fabrication processes by changing the refractive index parameters of the interposer material. By controlling the deposition thickness and material composition, the mirrors can be integrated into existing fabrication flows without requiring entirely new manufacturing techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach facilitates efficient wafer-level testing of PICs by allowing direct access to optical signals, reducing processing costs and improving the evaluation of sending and receiving devices, interconnect layers, and optical circuits.
Implementation Method 1
the upturned mirror structure... by reflecting signals perpendicularly to the substrate surface
Data Source
AI summary
A structure and method for the wafer level testing of interposer-based photonic integrated circuits is described that includes the formation of an upturned mirror structure and the method of utilizing the interposer-based mirror structure for electrical and optical testing of optoelectrical circuits that include emitting components such as lasers, detecting components such as photodetectors, and both emitting and detecting components. Electrical activation of the optoelectrical emitting or sending devices and the subsequent detection and measurement of the optical signals in detecting or receiving devices provides information on the operability or functionality of the PIC on the die at the wafer level, prior to die separation or singulation, using the electrical and optical components of the PIC circuit.