URTTLC Error Check Precision via Time-Divided CRC Polynomials
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Solution Overview
Problem
The existing wireless communication systems, particularly in the context of Ultra-Reliable and Low Latency Communications (URLLC) for 5G systems, face challenges in achieving high error check precision without increasing redundancy, as the number of CRC bits is not sufficient to meet the reliability demands of URLLC scenarios, leading to reduced transmission efficiency.
Innovation Solution
The method involves generating different check bit blocks for the same information bit block across multiple time windows using distinct CRC Cyclic Generator Polynomials, allowing for joint error checking without increasing the total number of CRC bits, effectively enhancing error check precision by combining check bit blocks from various transmissions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of CRC bits is increased to improve error check precision for URLLC, then transmission reliability is improved, but transmission efficiency is reduced due to excessive redundancy
Solution Approach 1:
The patent segments the error checking process across multiple time windows, where each window uses a different CRC cyclic generator polynomial to generate check bit blocks. Instead of using a single large CRC, the system divides the error checking into multiple smaller segments that are combined later, achieving high reliability without requiring excessive CRC bits in any single transmission.
Solution Approach 2:
The patent introduces a time dimension to the error checking process by distributing check bit blocks across multiple time windows. Rather than increasing CRC bits in a single dimension (spatial/redundancy), the system utilizes the time dimension to accumulate error checking capability, allowing multiple transmissions to contribute to the overall error detection precision.
2Measurement precision
If different CRC Cyclic Generator Polynomials are used in different time windows, then error check precision is enhanced through joint checking, but system complexity increases
Solution Approach 1:
The patent changes the parameter of the CRC generator polynomial across different time windows, using distinct polynomials (e.g., different degrees or coefficients) to generate check bit blocks. This parameter variation enhances error check precision by making the checking more robust against different error patterns, while the changes are systematically managed to control complexity.
Solution Approach 2:
The system employs a universal framework that can accommodate multiple CRC generator polynomials through a standardized process. The same basic CRC mechanism is reused across different time windows with different polynomial parameters, allowing the system to achieve enhanced error checking capability without proportionally increasing overall system complexity through systematic reuse of the same structural components.
Data Source
AI summary
The present disclosure provides a method and a device in a User Equipment (UE) and a base station for wireless communication. A first node transmits a first radio signal in a first time window, the first time window is any one time window of M time windows, the first radio signal carries a first check bit block. Herein, an information bit block corresponding to the first check bit block comprises a first bit block; values of bits comprised in the first check bit block are related to a position of the first time window in the M time windows, or, a total number of bits comprised in the first check bit block is or isn't related to a position of the first time window in the M time windows, the M is a positive integer greater than 1. The method improves precision of error correction without increasing redundancy.