USB Audio Asynchronous Feedback for Buffer-Centered Clock Sync

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Solution Overview

Problem

Current USB audio communication protocols, such as UAC 1.0 and UAC 2.0, face issues with asynchronous isochronous data synchronization due to quantization errors, buffer centering delays, and varying response times, leading to audio distortion and buffer underflow/overflow problems.

Innovation Solution

A method and system for generating asynchronous feedback information based on the relative change of stored samples and the relative phase of device and host clocks, allowing for more precise synchronization between the device and host, using a controller to adjust feedback values and account for clock differences and environmental changes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If quantized ratio feedback is used to indicate desired data rate, then feedback information can be transmitted using standard USB protocols, but quantization errors accumulate over time causing audio samples to underflow or overflow buffers

Engineering Contradiction:
Improvefeedback transmission compatibilityVSAvoidsynchronization accuracy
Core Design Contradiction:
Ease of operationVSManufacturing precision

Solution Approach 1:

The patent implements a feedback mechanism where the device sends buffer position information to the host, which then adjusts the sample rate accordingly. This continuous feedback loop allows for dynamic correction of synchronization drift without relying on quantized ratios, thereby preventing buffer underflow and overflow while maintaining compatibility with USB protocols.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent replaces the mechanical quantization process with a software-based phase-locked loop (PLL) that continuously tracks and adjusts the sample rate. This substitution eliminates the inherent precision loss of quantization by using floating-point arithmetic and continuous phase adjustment, achieving higher synchronization accuracy while maintaining protocol compatibility.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Device complexity

If delay in calculating clock ratios is allowed, then computational complexity is reduced, but loss of buffer centering increases leading to buffer underflow or overflow

Engineering Contradiction:
Improvecalculation complexityVSAvoidbuffer synchronization reliability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent performs preliminary calculations of clock ratios and buffer positions at predetermined intervals rather than continuously. This approach pre-calculates necessary adjustment parameters in advance, reducing real-time computational complexity while maintaining buffer centering through periodic updates that prevent drift accumulation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements periodic feedback transmission where the device sends buffer position information to the host at regular intervals. This periodic action reduces computational complexity by avoiding continuous calculations while maintaining synchronization reliability through timely updates that prevent buffer underflow and overflow conditions.

Inventive Principle:
Principle #19Periodic action

3Measurement precision

If measurement of SOF clock with respect to system clock is performed, then clock synchronization can be achieved, but variance occurs due to system interrupts making measurement difficult

Engineering Contradiction:
Improveclock ratio measurement accuracyVSAvoidclock measurement difficulty
Core Design Contradiction:
Measurement precisionVSDifficulty of detecting and measuring

Solution Approach 1:

The patent introduces a dedicated counter register as an intermediary between the SOF clock and system clock. This counter accumulates SOF periods without being affected by system interrupts, providing a stable measurement base. The counter acts as a buffer that isolates the measurement process from interrupt-induced variance, enabling accurate clock ratio calculation.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent creates a copy of the SOF clock signal in a dedicated counter register that is immune to system interrupts. This copied timing information can be measured independently without the variance introduced by interrupt handling, allowing for precise clock ratio measurement while maintaining system responsiveness to interrupts.

Inventive Principle:
Principle #26Copying

4Adaptability or versatility

If host response time to synchronization feedback is not specified, then USB protocol flexibility is maintained, but varying response times among different USB host implementations cause synchronization instability

Engineering Contradiction:
ImproveUSB protocol flexibilityVSAvoidsynchronization stability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent implements a dynamic feedback mechanism where the device continuously monitors buffer position and adjusts feedback transmission timing based on current synchronization needs. This dynamic approach allows the system to adapt to varying host response times while maintaining synchronization stability, as the feedback rate and content are adjusted in real-time according to actual buffer conditions rather than following a fixed schedule.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10651860B2Asynchronous positional feedback for asynchronous and isochronous communication
Publication Date: 2020.05.12 CIRRUS LOGIC INC
  • US10651860B2 patent drawing
  • US10651860B2 patent drawing
  • US10651860B2 patent drawing

AI summary

A method of generating asynchronous feedback information for asynchronous, isochronous audio communication may include determining a relative change of stored samples in a device and generating the asynchronous feedback information provided to a host from the device based on the relative change. A method of generating asynchronous feedback information for asynchronous, isochronous audio communication may include determining a relative phase of a host clock for a host and a device clock for a device and generating the asynchronous feedback information provided to the host from the device based on the relative phase.