Dynamic System Clock Adjustment for USB Bridge Power Optimization
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Solution Overview
Problem
In computer systems with multiple modules sharing a system clock, such as USB-to-SATA bridges, dynamically adjusting the processor clock rate based on load is insufficient, as all components must operate at matching clock rates for peak efficiency, leading to excessive power consumption during high performance demands.
Innovation Solution
A method to dynamically adjust the system clock rate by detecting commands and adjusting it to a fast speed when commands are received and to a slow speed when none are outstanding, ensuring all components operate efficiently while minimizing power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the system clock rate is increased to meet USB3.0 burst rate demands, then performance is improved, but power consumption increases significantly
Solution Approach 1:
The system dynamically adjusts the clock rate of the bridge chip based on real-time command queue status. When commands are detected in the queue, the clock rate is increased to fast speed to meet USB3.0 burst rate demands. When the queue is empty, the clock rate is reduced to slow speed to minimize power consumption. This dynamic adjustment resolves the contradiction between maintaining high performance and reducing power usage.
Solution Approach 2:
The invention changes the clock rate parameter of the bridge chip from a fixed high value to a variable value that switches between fast and slow speeds. This parameter change allows the system to optimize the balance between performance and power consumption by selecting the appropriate clock speed based on actual workload conditions.
2Use of energy by moving object
If the processor clock rate is reduced to save power, then power consumption decreases, but command processing delays increase
Solution Approach 1:
The system implements dynamic clock rate adjustment by monitoring the command queue status. When commands are present in the queue, the clock rate is immediately increased to fast speed to prevent processing delays. When the queue is empty, the clock rate is reduced to slow speed to save power. This dynamic response eliminates the trade-off between power savings and processing delays.
Solution Approach 2:
The invention employs feedback control by continuously monitoring the command queue status and adjusting the clock rate accordingly. The system detects when commands arrive and responds by increasing the clock rate, and detects when the queue is empty and responds by decreasing the clock rate. This feedback mechanism ensures that the system maintains optimal performance while minimizing power consumption.
Data Source
AI summary
In a first embodiment of the present invention, a method for dynamically adjusting a system clock of a plurality of system clock-controlled components in a system is provided, the method comprising: detecting the receipt of a command at a non-system clock-controlled component of the system; and adjusting the system clock to a fast speed based on the detecting. This embodiment may also include: determining that the command has been completed; determining that there are no outstanding commands in the plurality of system clock-controlled components; and adjusting the system clock to a slow speed based on the determination that there are no outstanding commands in the plurality of system clock-controlled components.