USB-C Power Delivery Protocol Hardware Acceleration
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Solution Overview
Problem
Existing USB-C power delivery protocols require significant code size and memory, leading to inefficient power delivery and high processing times, which is not optimized for low power and low code size requirements.
Innovation Solution
A system and method implementing a low power, low code size power delivery protocol on USB-C ports using a mix of analogue and digital components, with finite state machines, protocol timers, and power delivery message accelerator blocks, enabling compatibility with future USB-PD specifications and reducing code size through clock-gating and frequency reduction for low power utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If traditional USB-C power delivery protocol is implemented, then power delivery capability is achieved, but code size and memory requirements increase significantly
Solution Approach 1:
The patent segments the USB-PD protocol implementation into distinct hardware modules including state machine controllers, message queues, and protocol state machines. This modular segmentation allows the system to achieve full power delivery functionality while minimizing code size by distributing logic across dedicated hardware blocks rather than relying on large software implementations.
Solution Approach 2:
The patent replaces software-based protocol handling with hardware-based state machines and finite state machine controllers. This substitution of mechanical/software systems with hardware circuits dramatically reduces code size and memory requirements while maintaining complete USB-PD protocol functionality for power delivery negotiation and management.
2Power
If traditional USB-C power delivery protocol is implemented, then power delivery capability is achieved, but processing time increases
Solution Approach 1:
The patent implements preliminary action through pre-configured protocol state machines and pre-loaded message queues that prepare power delivery negotiation sequences in advance. The hardware state machines are pre-programmed with USB-PD protocol states, allowing immediate processing of power negotiation events without software interpretation delays, thus reducing processing time while maintaining full power delivery capability.
Solution Approach 2:
The patent replaces software-based protocol processing with hardware state machines that execute protocol logic in parallel. This hardware substitution eliminates software execution overhead and enables simultaneous processing of multiple power delivery negotiations across different USB-C ports, significantly reducing processing time while maintaining complete power delivery functionality.
3Power
If full USB-PD protocol functionality is implemented, then power delivery capability is improved, but hardware complexity increases
Solution Approach 1:
The patent implements universality through shared hardware resources including common state machine controllers, reusable message queues, and multiplexed protocol state machines that can handle multiple USB-C ports. This multi-functional design allows the system to support full USB-PD protocol functionality across multiple ports while minimizing hardware complexity through resource sharing rather than duplication.
Solution Approach 2:
The patent merges related protocol handling functions into integrated hardware blocks. The state machine controllers are combined with message queue management, and protocol state machines are integrated with power delivery negotiation logic. This merging of functions into unified hardware modules reduces overall hardware complexity while maintaining complete USB-PD protocol capability for power delivery.
Data Source
AI summary
Systems involve a dividing unit configured to divide functionality in digital hardware portion through finite state machines (FSMs), protocol timers and PD message accelerator blocks for reducing code size such that their implementation combined with a low code-size firmware (FW) interacts, using a control unit operatively coupled to the dividing unit, with the hardware portion to provide updates in an USB-PD specification, wherein at least one of the FSMs configured to run at a predefined UI clock frequency to enable low active power to the system, a wake-up unit running at least on 4 times of UI clock frequency and detects data edge on configuration channel line to wake-up the entire system from sleep state, wherein a plurality of standard power saving mechanisms selected from clock gating and frequency reduction for clocks are implemented to enable low power corresponding to the system and bypass paths at each level of implementation.