USB Type-C Power Delivery Throttling for Low-Latency SoC Control
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Solution Overview
Problem
Existing systems face delays and inefficiencies in throttling a System-on-Chip (SoC) due to latency in detecting charging power source presence or absence via VBUS rail, leading to ungraceful shutdowns and inadequate power management, especially with USB Type-C chargers providing varying power ranges.
Innovation Solution
Implementing a low latency Processor Throttle Control Indication (PTCI) signal with preemptive power connect-disconnect indication and net quantified energy availability, using USB Type-C and Power Delivery (PD) standards to trigger throttling actions based on charger connection or disconnection and peripheral device power changes, enabling fine-grain power budget adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If VBUS rail detection is used to detect charging power source presence or absence, then the system can detect power changes, but there is significant latency causing delays in throttling the SoC
Solution Approach 1:
The patent implements preemptive power connect-disconnect indication that triggers throttling actions before the actual power change occurs. The PD controller detects power source connection or disconnection and immediately generates PTCI signals to throttle the SoC, eliminating the detection latency inherent in VBUS rail monitoring. This preliminary action ensures the SoC is already throttled when power is actually lost, preventing ungraceful shutdowns.
2Productivity
If traditional VBUS detection method is used, then the system structure is simple, but the throttling response is delayed and cannot provide fine-grain power budget adjustments
Solution Approach 1:
The patent introduces a PD controller as an intermediary component between the power source and the SoC. This PD controller monitors power delivery protocol packets, detects power connect-disconnect events, and generates PTCI signals to throttle the SoC. While this adds a component, it enables fine-grain power budget adjustments and rapid throttling response that simple VBUS detection cannot provide.
Solution Approach 2:
The system implements feedback by monitoring USB Type-C and Power Delivery protocol packets to detect power source connection status and peripheral device power changes. This feedback mechanism provides real-time information about power availability, enabling the PD controller to generate appropriate PTCI signals for timely and proportional SoC throttling.
3Reliability
If VBUS rail detection is used, then the detection mechanism is simple, but it causes ungraceful shutdowns due to latency in responding to power source disconnection
Solution Approach 1:
The preemptive power connect-disconnect indication mechanism detects power source disconnection through PD protocol packets before the actual power is lost. Upon detection, the PD controller immediately generates PTCI signals to throttle the SoC, ensuring graceful shutdown by reducing power consumption in advance. This eliminates the latency problem where the system only reacts after VBUS voltage drops, which is too late to prevent ungraceful shutdown.
Data Source
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AI summary
A software and hardware architecture framework utilize the specifications of Universal Serial Bus (USB) Type-C and Power Deliver (PD) to provide fine grain throttling of a processor (e.g., system-on-chip (SoC)) (101). Based on an external charger connection or disconnection (123), a low latency fine grain power budget loss or gain indication to the processor is delivered. The mechanism of various embodiments is also applicable to connection or disconnection of VBUS powered peripheral devices to the system. The net power loss or gain available to the SoC and System is proportionally used to scale the processor throttling.