USB Cache Management for Host Memory Latency Reduction

The patent segments the cache into multiple cache lines, where each cache line can be independently assigned to different device endpoints. This segmentation allows the limited cache volume to be dynamically shared among multiple transfer rings, enabling efficient utilization of the constrained cache resource while maintaining low latency for multiple endpoints simultaneously.

The patent implements dynamic cache line assignment where cache lines are not permanently bound to specific device endpoints but are instead allocated on-demand based on current transfer needs. The host controller can assign and reassign cache lines to different endpoints as transfer rings become active or inactive, allowing the cache to adapt to varying workload patterns and maximize the utilization of limited cache volume.

The patent implements a self-service cache management mechanism where the host controller autonomously manages cache line assignment without requiring complex external control logic. The host controller monitors its own transfer ring status and automatically assigns cache lines to active endpoints and reclaims them when endpoints become inactive, simplifying the overall system architecture while maintaining high cache utilization.

The patent employs a discard and recover strategy for cache line management. When a device endpoint becomes inactive or its transfer ring is completed, the associated cache line is discarded from its current assignment and made available for recovery and reuse by other active endpoints. This approach maximizes cache utilization by ensuring that cache lines are continuously reused rather than remaining idle, while keeping the management mechanism relatively simple through automatic tracking of endpoint activity states.