USB Clock Synchronization Using TSEQ Training and Clock Recovery

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Solution Overview

Problem

The universal serial bus (USB) protocol's reference clock signal is not synchronized with the transmission frequency of the host unit, necessitating an elastic buffer to compensate for frequency differences, which is costly and inefficient.

Innovation Solution

A clock-synchronized method that synchronizes the host unit's clock signal with the controlled device's clock signal using a sequence of training signals (TSEQ) and a clock/data recovery device, eliminating the need for a conventional clock circuit and elastic buffer by aligning the clock signals of the host unit, receiver, and transmitter according to the USB protocol.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If an independent crystal oscillator or oscillation circuit is installed in the receiver and transmitter for providing a reference clock signal, then the data transmission and reception can be performed, but the reference clock signal is not synchronized to the transmission frequency of the host unit, requiring an elastic buffer which increases device complexity and cost

Engineering Contradiction:
Improvedata transmission reliabilityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the clock signal directly from the incoming data stream using a clock and data recovery device, eliminating the need for independent crystal oscillators and elastic buffers. The receiver extracts the clock signal from the transmitted data, thereby removing the separate clock generation components and reducing device complexity while maintaining reliable data transmission.

Inventive Principle:
Principle #2Taking out (Extraction)

2Reliability

If an elastic buffer is disposed in the electronic product to buffer the frequency difference between reference clock signal and transmission frequency, then frequency synchronization can be achieved, but the device complexity and cost increase

Engineering Contradiction:
Improvefrequency synchronizationVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent removes the elastic buffer by extracting the clock signal directly from the incoming data stream. The clock and data recovery device recovers both clock and data signals simultaneously from the transmitted stream, eliminating the need for separate frequency buffering mechanisms while achieving frequency synchronization.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The clock and data recovery device acts as an intermediary that directly converts the incoming data stream into synchronized clock and data signals, replacing the traditional elastic buffer mechanism. This intermediary device achieves frequency synchronization without requiring separate buffering components.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If conventional clock circuits and elastic buffers are used for clock synchronization, then clock signals can be generated, but additional buffering components are required which increases cost

Engineering Contradiction:
Improveclock signal generationVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent eliminates conventional clock circuits and elastic buffers by extracting the clock signal directly from the incoming data stream. This approach removes additional buffering components from the bill of materials, reducing manufacturing cost while ensuring reliable clock signal generation for data transmission.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS8553753B2Clock-synchronized method for universal serial bus (USB)
Publication Date: 2013.10.08 GENESYS LOGIC INC
  • US8553753B2 patent drawing
  • US8553753B2 patent drawing
  • US8553753B2 patent drawing

AI summary

A clock-synchronized method for universal serial bus (USB) is described. The method includes the following steps of: (a) a transmitter sends a periodic signal to a host unit during a first time interval; (b) the host unit transmits a first equalization training sequence signal to a receiver during a second time interval to train the receiver and the transmitter continuously sends the periodic signal to the host unit; (c) a clock and data recovery device extracts the first equalization training sequence signal during the second time interval to generate a extracted clock signal and a data signal; and (d) the transmitter sends a second equalization training sequence signal to the host unit based on the extracted clock signal during the third time interval to train the host unit and the receiver and the transmitter commonly utilize the extracted clock signal as a reference clock.