Pause/Go USB Data Ingestion for High-Rate Capture on Constrained MCUs

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Solution Overview

Problem

Low-cost MCUs like ARM Cortex M4 are unable to process high-rate USB 2.0 data such as 60 FPS HD video due to CPU and memory constraints, leading to performance limitations and increased system complexity when using higher capability MCUs or dedicated peripherals.

Innovation Solution

A constrained master controller unit system with a data ingester and data processor that processes data in a pause/go/pause sequence, utilizing a header preview to optimize data ingestion and processing, decoupling raw data ingestion from higher-protocol processing to minimize memory copies and CPU load.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If higher capability MCUs or dedicated peripheral controllers are used to process high-rate USB data, then data processing capability is improved, but system cost and complexity increase

Engineering Contradiction:
Improvedata processing capabilityVSAvoidsystem complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The system segments the data processing task into two distinct components: a data ingester that handles high-speed USB data reception and a data processor that performs application-level processing. This segmentation allows the constrained MCU to offload the bandwidth-intensive ingestion task to a dedicated hardware module, thereby maintaining high data processing capability while reducing the computational burden on the main CPU and simplifying the overall system architecture.

Inventive Principle:
Principle #1Segmentation

2Productivity

If higher capability MCUs are used to process high-rate USB data, then data processing capability is improved, but system cost increases

Engineering Contradiction:
Improvedata processing capabilityVSAvoidsystem cost
Core Design Contradiction:
ProductivityVSEase of manufacture

Solution Approach 1:

By segmenting the data processing function into a dedicated data ingester module and a data processor, the system enables the use of lower-cost, constrained MCUs that would otherwise be incapable of handling high-rate USB data. The data ingester handles the computationally intensive task of receiving and buffering high-speed USB data, allowing the main MCU to remain simple and cost-effective while still achieving the required data processing capability.

Inventive Principle:
Principle #1Segmentation

3Productivity

If the data processor continuously receives high-rate USB data, then data processing capability is improved, but CPU load increases

Engineering Contradiction:
Improvedata processing capabilityVSAvoidCPU load
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The system divides the data handling responsibilities between the data ingester and the data processor. The data ingester continuously receives high-rate USB data and stores it in a buffer, while the data processor retrieves data from this buffer at its own pace. This segmentation eliminates the need for the CPU to be continuously engaged in high-speed data reception, thereby reducing CPU load and energy consumption while maintaining the ability to process high-rate data streams.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The data processor operates in periodic cycles, retrieving data from the buffer at intervals rather than continuously. This periodic operation allows the CPU to remain idle or perform other tasks between data retrieval cycles, significantly reducing average CPU load and energy consumption compared to continuous processing, while still maintaining the throughput required for high-rate USB data.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentEP4327550B1Capture of high bandwidth rate USB data in constrained MCU environments
Publication Date: 2025.08.06 JABIL INC
  • EP4327550B1 patent drawingFigure 1
  • EP4327550B1 patent drawingFigure 2
  • EP4327550B1 patent drawingFigure 3~4

AI summary

A constrained master controller unit system for use in an internet-of-things device that applies machine learning. The system includes at least a data ingester; a data processor operable alternately with the data ingester in a respective pause/go/pause/go and go/pause/go/pause matched sequence; and a header preview for incoming data, wherein parameters, including at least timing and data volume, for the matched sequence are automatically selected based on the header preview. The non-header data is not processed by the header preview, and is processed by the data processor only during one of its respected go matched sequence.