USB 2.0 Legacy Driver Using Segmented Parallel Output Stages
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Solution Overview
Problem
Conventional USB 2.0 transceivers face challenges in meeting the rise time and crossing voltage requirements for full-speed and low-speed modes due to the use of large capacitors that increase size and cost, and CMOS inverters with unequal pull-up and pull-down strengths, leading to out-of-spec crossing voltages.
Innovation Solution
Implementing a legacy full-speed/low-speed USB driver using multiple parallel output stages with a shift register to sequentially provide USB data, allowing for precise control of rise times and crossing voltages, and optionally incorporating slew-limiting elements to minimize stair-stepping in the signal waveform.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a large output capacitor is used to reduce output slew rate, then rise time control is improved, but device area and cost increase
Solution Approach 1:
The patent divides the single large output capacitor into multiple smaller capacitors distributed across parallel output stages. Each stage has its own smaller capacitor, and the combined effect of multiple stages achieves the required slew rate control without requiring a single large capacitor, thereby reducing overall device area while maintaining rise time performance.
Solution Approach 2:
The patent transitions from a single-dimension solution (one large capacitor) to a multi-dimensional approach by distributing capacitance across multiple parallel output stages. This spatial distribution allows the system to achieve the same electrical effect with reduced area by utilizing multiple smaller elements arranged in parallel rather than one large element.
2Manufacturing precision
If a large output capacitor is used to reduce output slew rate, then rise time control is improved, but manufacturing cost increases
Solution Approach 1:
The patent segments the large capacitor requirement into multiple smaller capacitors that can be more easily manufactured with standard semiconductor processes. Smaller capacitors have better process control and yield, reducing manufacturing cost while achieving the same overall capacitance effect through parallel combination across multiple output stages.
3Speed
If CMOS inverter is used with unequal pull-up and pull-down strengths, then switching speed is improved, but crossing voltage control deteriorates
Solution Approach 1:
The patent divides the single inverter into multiple parallel output stages, each with its own inverter and capacitor. This segmentation allows the unequal pull-up and pull-down strengths of individual CMOS inverters to be distributed and averaged across multiple stages, improving crossing voltage control while maintaining the speed advantages of CMOS switching.
Solution Approach 2:
The patent combines multiple parallel output stages with identical or similar characteristics to achieve an averaged output effect. By merging the outputs of multiple stages, the system benefits from both the fast switching of CMOS inverters and the improved crossing voltage control that results from averaging out process variations across multiple devices.
4Area of stationary object
If Miller capacitor is used instead of output capacitor, then device area is reduced, but capacitance control precision deteriorates
Solution Approach 1:
The patent uses multiple smaller capacitors in parallel across output stages rather than a single large capacitor or Miller capacitor. This segmentation allows for better capacitance control precision because each smaller capacitor can be more accurately manufactured with standard processes, and the parallel combination maintains the required total capacitance with improved overall precision.
Data Source
AI summary
A Universal Serial Bus (USB) 2.0 transceiver includes a legacy full speed and low speed (FS/LS) USB driver that includes multiple output stages. The multiple output stages are connected in parallel to an output terminal. By sequentially providing the USB data to the multiple output stages, the USB signal at the output terminal will transition between logic states in an incremental fashion as the multiple output stages sequentially switch their individual output states. Consequently, the rise/fall time for the legacy FS/LS USB driver is controlled not by the strength of the inverter transistors in the output stages, but rather by the number of stages and the time interval between application of the USB data to each stage. Therefore, by selecting an appropriate number of output stages and an appropriate timing interval, accurate control over full speed and low speed USB signal rise/fall times can be provided.