Single Chip USB 2.0 and eUSB2 Transceiver with Dynamic Mode Switching

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Solution Overview

Problem

Current technologies require separate integrated chips for USB 2.0 and eUSB2 connectivity, leading to increased area and power overhead, and lack flexibility in switching between standards based on connected components.

Innovation Solution

A single integrated chip that facilitates both USB 2.0 and eUSB2 communication, allowing for switching between standards based on detected voltage levels or control signals, and sharing components like transceiver combination circuitry and power supply voltages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If separate integrated chips are used for USB 2.0 and eUSB2 connectivity, then each standard can be implemented with dedicated optimized circuitry, but the total chip area and power consumption increase

Engineering Contradiction:
Improvestandard compatibilityVSAvoidchip area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent combines USB 2.0 and eUSB2 connectivity into a single integrated chip that can operate in both modes. The transceiver circuitry is designed to support both USB 2.0 differential signaling and eUSB2 single-ended signaling through configuration control, eliminating the need for separate chips and reducing overall chip area while maintaining full compatibility with both standards

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The integrated transceiver is designed with universal functionality to support multiple communication modes (USB 2.0 high-speed differential mode and eUSB2 single-ended mode) within a single chip. The circuitry can be configured via control signals to operate in either mode, providing multi-standard support without requiring separate dedicated hardware for each standard

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If separate integrated chips are used for USB 2.0 and eUSB2 connectivity, then each standard has dedicated optimized circuitry, but power consumption increases

Engineering Contradiction:
Improvestandard compatibilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The patent merges USB 2.0 and eUSB2 transceiver functions into a single integrated circuit block, sharing common components such as voltage regulators, signal buffers, and control logic. This consolidation eliminates redundant power consumption from duplicate circuitry and allows dynamic power management where only the active standard's circuitry consumes power at any given time

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The universal transceiver design uses a single set of power management circuits that can serve both USB 2.0 and eUSB2 modes. Power is dynamically allocated based on the active communication mode, with control logic enabling or disabling specific circuit paths to minimize power consumption while maintaining full functionality for both standards

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Area of stationary object

If a single integrated chip supports both USB 2.0 and eUSB2, then area and power are reduced, but the complexity of switching between standards increases

Engineering Contradiction:
Improvechip areaVSAvoidswitching control complexity
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The patent implements dynamic switching between USB 2.0 and eUSB2 modes using control signals that reconfigure the transceiver circuitry in real-time. The switching mechanism dynamically adjusts impedance matching, signal routing, and termination based on the detected or commanded operating mode, allowing flexible adaptation without manual intervention or complex external control logic

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The integrated transceiver includes built-in detection and switching logic that automatically identifies the required operating mode and configures itself accordingly. The circuitry monitors input conditions, detects the presence of USB 2.0 or eUSB2 signaling characteristics, and autonomously switches between modes without requiring external control logic, thereby simplifying the overall system complexity

Inventive Principle:
Principle #25Self-service

4Area of stationary object

If a single integrated chip supports both USB 2.0 and eUSB2, then area is reduced, but the difficulty of detecting and measuring operating mode increases

Engineering Contradiction:
Improvechip areaVSAvoidmode detection difficulty
Core Design Contradiction:
Area of stationary objectVSDifficulty of detecting and measuring

Solution Approach 1:

The patent incorporates feedback mechanisms where the transceiver monitors its own operating conditions and signals back to a control logic unit to determine the active mode. By detecting voltage levels, signal characteristics, or control bit states on the data lines, the system receives feedback about the connected device type and automatically configures the appropriate signaling mode, making mode detection straightforward and reliable

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS9836420B2Integrated systems with universal serial Bus 2.0 and embedded universal serial Bus 2 connectivity
Publication Date: 2017.12.05 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US9836420B2 patent drawing
  • US9836420B2 patent drawing
  • US9836420B2 patent drawing

AI summary

An integrated circuit is provided. The integrated circuit includes a mapping circuit configured to determine a state associated with a first universal series bus (USB) communication mode based on one or both of a signal level on a first data line and a signal level on a second data line. The integrated circuit also includes a line state converter circuit configured to generate a line state associated with a second USB communication mode based on the determined state and based on one or both of the signal level on the first data line and the signal level on the second data line.