USB Flash Disk Startup Method for Synchronous Memory Phase Calibration
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Solution Overview
Problem
Conventional USB flash disks with synchronous flash memory face challenges in startup speed and stability due to varying phase parameters of reading data, leading to unreliable operations as the capacity increases and the low read/write frequency is insufficient for newer USB3.0 standards.
Innovation Solution
A start-up method for USB flash disks involves writing test data into a data cache zone, comparing it with the USB controller's memory zone, adjusting the read/write clock phase to ensure synchronization, and selecting the optimal phase for reliable data access, utilizing a frequency multiplier and delay circuit to calibrate the clock phase for stable operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a low read write frequency (about 10 MHz) is used to access flash memory, then reliability of data reading is improved, but start-up time increases and productivity decreases
Solution Approach 1:
The patent applies preliminary action by performing phase calibration before normal data operations. The system pre-determines the optimal phase parameter through test data comparison, storing this calibration information for subsequent use. This preliminary phase adjustment ensures that when high-frequency access is needed, the system is already optimized for reliable reading, thus resolving the contradiction between speed and reliability.
Solution Approach 2:
The patent changes the phase parameter of the read write clock dynamically. By adjusting the phase parameter based on comparison results between test data in flash memory and RAM, the system optimizes the timing characteristics for high-frequency operation. This parameter adjustment enables reliable data reading at higher frequencies (up to 80 MHz), thereby reducing start-up time while maintaining reliability.
2Productivity
If synchronous flash memory with high working frequency (up to 80 MHz) is used, then productivity and start-up speed are improved, but reliability deteriorates due to phase parameter variations among different memory chips
Solution Approach 1:
The patent dynamically adjusts the phase parameter of the read write clock based on empirical testing. By comparing test data read from flash memory with stored test data in RAM, the system determines the optimal phase parameter that ensures reliable reading for that specific memory chip. This parameter optimization enables the system to achieve high data access speeds (up to 80 MHz) while maintaining reading reliability, thus resolving the contradiction between productivity and reliability.
Solution Approach 2:
The patent implements a feedback mechanism where the system reads test data from flash memory, compares it with stored test data in RAM, and uses the comparison result to adjust the phase parameter. This closed-loop feedback process ensures that the system automatically optimizes the phase parameter for each specific memory chip, enabling reliable high-speed operation and resolving the reliability issues associated with phase parameter variations among different chips.
3Speed
If the read write frequency is increased from 10 MHz to 80 MHz, then start-up speed is improved, but the complexity of phase calibration increases
Solution Approach 1:
The patent applies self-service by enabling the system to automatically perform phase calibration without external intervention. The flash memory controller autonomously writes test data, reads it back, compares results with stored test data in RAM, and adjusts the phase parameter based on the comparison. This self-calibrating mechanism simplifies the overall system complexity while enabling high-speed operation, as the calibration process is integrated into the controller's startup sequence and requires no additional external calibration equipment or complex external control logic.
Data Source
AI summary
A start-up method for USB disk with synchronous flash memory includes steps of: (a) writing test data into a data cache zone of a flash memory according to an initiate read write clock of a flash memory controller; (b) reading the test data to a memory zone of a USB controller; (c) comparing the test data in two memory zones, and recording a comparison result and a phase parameter of read write clock; (d) delaying the initiate read write clock for one-unit delay, and repeating steps (a)˜(d); (e) if the comparison result changes from success to failure, stopping repeat the step (d); (f) selecting the phase parameter of the read write clock that corresponds to one of the comparison results in an interval with multiple continuous successful comparison results to determine a clock phase for accessing the flash memory, and then starting up the USB flash disk. The method is quick and stable.