USB Host Controller Dual-Controller Shared Memory Architecture
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Solution Overview
Problem
Existing USB host controllers face challenges in efficiently managing high-speed data transfers between USB devices and the host, particularly in ensuring compatibility and minimizing memory over-run or under-run issues while supporting both periodic and asynchronous transfers.
Innovation Solution
A USB host controller design incorporating multiple controllers and memories, with direct memory access (DMA) engines, that prioritizes periodic transfers and utilizes shared memory resources to optimize data transfer stages, ensuring efficient handling of both periodic and asynchronous data packets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a USB host controller supports both periodic and asynchronous transfers simultaneously, then transfer versatility is improved, but device complexity increases due to multiple controllers and memory management
Solution Approach 1:
The patent merges periodic and asynchronous transfer functionalities into a single USB host controller by integrating a first controller for periodic transfers and a second controller for asynchronous transfers. Both controllers share common resources including memory, DMA engine, and interrupt handling mechanisms, thereby reducing overall device complexity while maintaining versatility
Solution Approach 2:
The controller design implements multi-functionality where the first controller handles periodic transfers (isochronous and interrupt) and the second controller handles asynchronous transfers (control and bulk). Both controllers utilize shared memory and DMA resources, allowing a single controller unit to perform multiple transfer types without requiring separate dedicated hardware for each function
2Reliability
If memory capacity is increased to prevent over-run and under-run issues, then transfer reliability is improved, but device complexity and cost increase
Solution Approach 1:
The patent segments the memory into multiple distinct regions: a first memory region allocated for periodic transfers and a second memory region allocated for asynchronous transfers. Each region is independently managed by its respective controller, allowing optimized memory allocation and preventing over-run/under-run issues without requiring excessive total memory capacity
Solution Approach 2:
The controller performs preliminary actions by pre-allocating specific memory regions for different transfer types before data transfer begins. The first controller is pre-configured with access to the first memory region for periodic transfers, and the second controller is pre-configured with access to the second memory region for asynchronous transfers, ensuring proper memory management from the outset
3Reliability
If separate memory regions are allocated for periodic and asynchronous transfers, then transfer reliability is improved by preventing memory conflicts, but device complexity increases
Solution Approach 1:
While allocating separate memory regions for different transfer types, the patent merges the memory management system by implementing a unified memory interface and shared DMA engine that serves both the first and second controllers. This approach ensures reliable memory access for each transfer type while avoiding the complexity of completely separate memory subsystems
Data Source
AI summary
The present invention provides a USB host controller and control method thereof. The USB host controller comprises a first controller, a second controller and a first memory. The first controller controls first transfer between a host and a USB device. The second controller controls second transfer between the host and the USB device. The first memory is coupled to the first controller and the second controller and is configured to temporarily store data transferred between the host and the USB device. The first controller accesses the first memory during the first transfer, and the second controller accesses the first memory during the second transfer.