USB Host Controller Ping-Pong Buffering for Data Transfer
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Solution Overview
Problem
Existing data transfer methods over bus systems, such as USB, require processor intervention to achieve high data transfer rates, limiting efficiency.
Innovation Solution
A method involving the formation of transfer descriptors with headers and payload data, stored in a buffer memory, where data is read cyclically from paired transfer descriptors, allowing high-rate data transfer without processor intervention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If ping-pong buffering is used to increase data transfer rate, then data transfer rate is improved, but processor intervention is required which reduces system efficiency
Solution Approach 1:
The host controller is designed to automatically manage ping-pong buffering operations without requiring processor intervention. The controller autonomously switches between paired transfer descriptors and manages data flow between FIFO buffers, enabling the system to self-regulate high-speed data transfer while eliminating the need for processor involvement in buffer management operations.
2Reliability
If multiple transfer descriptors are used to maintain data order, then data integrity is improved, but device complexity increases
Solution Approach 1:
The data transfer process is segmented into multiple transfer descriptors, each representing a discrete data unit with its own header and payload. This segmentation allows the host controller to manage complex data ordering requirements through structured, modular descriptors while simplifying the overall control logic by breaking down the transfer process into manageable segments that can be independently tracked and transmitted.
Data Source
AI summary
A method of transferring bulk and control data from a first device to a second device over a USB bus comprises storing transfer descriptors, each including a transfer descriptor header and payload data, in a buffer memory in the first device. The data is read in packets for transfer to the second device, with packets being read from the transfer descriptors cyclically. When the first and second transfer descriptor headers, in first and second transfer descriptors respectively, define a common endpoint, data packets are read from only the first transfer descriptor, until such time as it is detected that all data packets from the first transfer descriptor have been transmitted, and thereafter data packets are read from the second transfer descriptor.