USB Ordered Set Decoder for Incremental FEC Synchronization

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Low-level embedded devices such as repeaters and retimers face challenges in parsing USB messages due to memory and processing limitations, particularly in handling forward error correction and maintaining synchronization with sync bits, which can lead to errors and failure in data reception.

Innovation Solution

A method that parses USB messages incrementally, using pattern matching to identify unscrambled and scrambled ordered sets on the fly, reducing the need for full buffering and computational resources, and dynamically managing the descrambler state to maintain synchronization and correct errors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If full buffering of USB message frames is implemented, then message parsing accuracy is improved, but memory requirements and device complexity increase significantly

Engineering Contradiction:

Improvemessage parsing accuracyVSAvoidmemory requirements

Core Design Contradiction:

Measurement precisionVSQuantity of substance

Solution Approach 1:

The patent divides the USB message frame into multiple super symbols and processes them incrementally as they arrive. Instead of buffering the entire frame, the system parses each super symbol sequentially, using pattern matching to identify ordered sets and validate messages on-the-fly. This segmentation approach maintains parsing accuracy while dramatically reducing memory requirements from full-frame buffering to minimal per-symbol processing buffers.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary pattern matching and validation operations on incoming super symbols before complete frame assembly. By pre-identifying ordered set patterns and performing preliminary error checking incrementally, the system avoids the need to store entire frames for later processing, thereby reducing memory requirements while maintaining parsing accuracy.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If full forward error correction computation is performed, then error detection and correction capability is improved, but processing power requirements and computational complexity increase

Engineering Contradiction:

Improveerror detection and correction capabilityVSAvoidprocessing power requirements

Core Design Contradiction:

ReliabilityVSPower

Solution Approach 1:

The patent implements partial FEC computation by performing incremental error checking and validation on individual super symbols and ordered sets as they are received, rather than computing full FEC on the entire message frame. This partial action approach provides sufficient error detection and correction capability for critical segments while significantly reducing the processing power and computational complexity required compared to complete frame-level FEC.

Inventive Principle:

Principle #16Partial or excessive action

3Quantity of substance

If incremental pattern matching is used to identify USB messages, then memory usage is reduced, but the complexity of real-time pattern recognition and synchronization increases

Engineering Contradiction:

Improvememory usageVSAvoidpattern recognition complexity

Core Design Contradiction:

Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent employs self-synchronizing ordered set patterns with predefined synchronization identifiers that automatically indicate message boundaries and types. The incremental pattern matching system uses these self-identifying patterns to maintain synchronization without requiring complex external control logic or large buffers to track message state, thereby reducing memory usage while managing recognition complexity through the inherent structure of the protocols.

Inventive Principle:

Principle #25Self-service

4Measurement precision

If sync bits are used for message synchronization, then message boundary detection is improved, but synchronization loss and false identifications may occur due to errors

Engineering Contradiction:

Improvemessage boundary detection precisionVSAvoidsynchronization reliability

Core Design Contradiction:

Measurement precisionVSReliability

Solution Approach 1:

The patent incorporates feedback mechanisms where each received super symbol is validated against expected ordered set patterns, and synchronization status is continuously monitored and adjusted. When synchronization errors or false identifications are detected through pattern validation failures, the system can detect and correct sync bit errors using forward error correction, providing feedback-driven synchronization recovery that improves reliability while maintaining precise boundary detection.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS11658771B2Error-tolerant forward error correction ordered set message decoder

Publication Date: 2023.05.23 KANDOU LABS SA

AI summary

Methods are described for identifying and acting upon predetermined message patterns during reception of a data stream structured as USB message frames. A first embodiment performs pattern matching between received message bits and one or more predetermined sequences, identifying unscrambled ordered set messages. A second embodiment applies a descrambling operation and performs comparable pattern matching between descrambled received message bits and one or more additional predetermined sequences, identifying scrambled ordered set messages.