USB Ordered Set Decoder for Incremental FEC Parsing

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Solution Overview

Problem

Low-level embedded devices such as repeaters and retimers face challenges in parsing USB messages due to memory and processing limitations, particularly in handling forward error correction and maintaining synchronization with scrambled data streams, which can lead to errors and failure in data reception.

Innovation Solution

The solution involves parsing USB messages incrementally as they are received, using pattern matching to identify unscrambled and scrambled ordered sets, and dynamically managing the descrambler state to reduce memory and processing requirements, allowing for on-the-fly processing and error correction without the need for full frame buffering.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If full frame buffering is implemented to parse USB messages, then message parsing accuracy is improved, but memory requirements and device complexity increase significantly

Engineering Contradiction:
Improvemessage parsing accuracyVSAvoidmemory requirements
Core Design Contradiction:
Measurement precisionVSQuantity of substance

Solution Approach 1:

The patent segments the USB message frame into individual super symbols and processes them incrementally as they are received. Instead of buffering the entire frame, the system parses each super symbol separately, using pattern matching on received bits to identify message types. This segmentation allows accurate message parsing while minimizing memory requirements to only what is needed for current symbol processing.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary pattern matching operations on incoming super symbols to identify potential message types before complete frame reception. By预先 comparing received patterns against known message patterns and using sync bit detection, the system can begin processing and identifying messages incrementally, rather than waiting to buffer the entire frame first.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If forward error correction computation is performed for every detected error, then data integrity is improved, but processing power requirements and computational load increase

Engineering Contradiction:
Improvedata integrityVSAvoidprocessing power requirements
Core Design Contradiction:
ReliabilityVSPower

Solution Approach 1:

The patent applies partial error correction by performing FEC computation only when specifically needed rather than for every possible error condition. The system uses pattern matching and sync bit validation to identify likely valid messages, and only initiates full FEC computation when errors are detected in critical areas. This selective approach maintains data integrity while reducing overall processing power requirements.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The patent replaces heavy mechanical computation with lighter logical operations. Instead of performing full FEC computation as a default mechanical process, the system uses pattern matching logic, bitwise comparisons, and sync bit detection to identify valid messages. This substitution of computational mechanics reduces processing power requirements while maintaining error correction capabilities.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Productivity

If sync bit state is used to facilitate message parsing, then parsing efficiency is improved, but synchronization errors can propagate and cause failure in data reception

Engineering Contradiction:
Improveparsing efficiencyVSAvoidsynchronization reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent implements feedback mechanisms where the received sync bits are continuously monitored and validated against expected patterns. When sync bits indicate a potential message boundary, the system performs pattern matching validation to confirm the identification. This feedback loop allows the system to maintain parsing efficiency while detecting and correcting synchronization errors, preventing error propagation that would occur with blind sync bit following.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11356197B1Error-tolerant forward error correction ordered set message decoder
Publication Date: 2022.06.07 KANDOU LABS SA
  • US11356197B1 patent drawing
  • US11356197B1 patent drawing
  • US11356197B1 patent drawing

AI summary

Methods are described for identifying and acting upon predetermined message patterns during reception of a data stream structured as USB message frames. A first embodiment performs pattern matching between received message bits and one or more predetermined sequences, identifying unscrambled ordered set messages. A second embodiment applies a descrambling operation and performs comparable pattern matching between descrambled received message bits and one or more additional predetermined sequences, identifying scrambled ordered set messages.