USB Ordered Set Decoder With On-the-Fly FEC and Descrambler Sync

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Solution Overview

Problem

Low-level embedded devices such as repeaters and retimers face challenges in parsing USB messages due to memory and processing limitations, particularly in handling forward error correction and maintaining synchronization when errors occur, which can lead to failure in identifying unscrambled ordered sets and maintaining descrambler synchronization.

Innovation Solution

The solution involves parsing super symbols on the fly as they are received, using pattern matching to identify unscrambled and scrambled ordered sets, and dynamically managing the descrambler state to reduce memory and processing requirements, allowing for incremental FEC parity calculation and reduced computational needs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional USB message parsing is used in low-level embedded devices, then accurate message identification can be achieved, but memory and processing power requirements become prohibitively high

Engineering Contradiction:
Improvemessage identification accuracyVSAvoidmemory and processing requirements
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The USB message frame is divided into super symbols that are processed incrementally as they arrive. Instead of buffering the entire frame, the parser processes super symbols in sequence, using pattern matching on partial data to identify message types. This segmentation allows embedded devices with limited memory to parse messages without requiring full-frame buffering.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system performs preliminary pattern matching on incoming super symbols to identify potential message types before complete frame reception. By pre-defining patterns for different USB message types and performing incremental matching, the system can begin identification early in the reception process, reducing the need to wait for and store the entire frame.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If full forward error correction computation is performed on every received frame, then error correction reliability is improved, but processing time and computational resources increase significantly

Engineering Contradiction:
Improveerror correction reliabilityVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

Instead of performing complete FEC computation on every frame, the system performs partial FEC checks only when pattern matching indicates a potential message match. This selective approach applies error correction resources only when needed, rather than uniformly processing all received data, thereby reducing overall processing time while maintaining reliability for identified messages.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The system uses pattern matching results as feedback to control FEC computation. When pattern matching identifies a potential USB message, this triggers FEC verification. The feedback loop between pattern matching and FEC computation ensures that error correction is applied selectively based on actual message content, optimizing the balance between reliability and processing efficiency.

Inventive Principle:
Principle #23Feedback

3Measurement precision

If sync bits are used to confirm message identification, then false identifications are reduced, but the system becomes more sensitive to synchronization errors and timing variations

Engineering Contradiction:
Improvemessage identification accuracyVSAvoidsynchronization robustness
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The system uses pattern matching as a preliminary filter before relying on sync bits for confirmation. By pre-identifying potential messages through pattern matching on the message body itself, the system creates a cushion against synchronization errors. This preliminary identification step reduces dependence on perfectly timed sync bits, making the system more robust to timing variations while maintaining identification accuracy.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS12009919B2Error-tolerant forward error correction ordered set message decoder
Publication Date: 2024.06.11 KANDOU LABS SA
  • US12009919B2 patent drawing
  • US12009919B2 patent drawing
  • US12009919B2 patent drawing

AI summary

Methods are described for identifying and acting upon predetermined message patterns during reception of a data stream structured as USB message frames. A first embodiment performs pattern matching between received message bits and one or more predetermined sequences, identifying unscrambled ordered set messages. A second embodiment applies a descrambling operation and performs comparable pattern matching between descrambled received message bits and one or more additional predetermined sequences, identifying scrambled ordered set messages.