USB Oscillator Frequency Adjustment via Delay Lock Loop
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Solution Overview
Problem
Conventional devices, such as phase lock loops (PLL), face challenges in synchronizing bit-rates of data streams in USB data transmission due to long lock times and require accurate circuits to avoid clock errors and erroneously fetched reference signals, which is not efficiently addressed by existing technologies.
Innovation Solution
The proposed solution involves a built-in oscillator for USB interfaces using a delay lock loop (DLL), an error compare module, a computation module, and frequency dividers to adjust oscillation frequency based on quantitative codes derived from error time quantification, eliminating the need for high frequency timing and long packet data reference signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If PLL architecture is used for frequency adjustment, then frequency synchronization can be achieved, but lock time becomes excessively long and circuit accuracy requirements increase
Solution Approach 1:
The frequency adjustment process is divided into two distinct stages: coarse tuning (using 4-bit reference data) and fine tuning (using 20-bit reference data). This segmentation allows the system to quickly achieve approximate synchronization followed by precise adjustment, significantly reducing overall lock time while maintaining accuracy.
Solution Approach 2:
The coarse tuning circuit performs preliminary frequency adjustment before fine tuning begins. By pre-establishing a rough frequency match using fewer reference bits, the system reduces the time required for subsequent fine tuning, thereby decreasing total lock time.
2Measurement precision
If coarse tuning and fine tuning circuits are used for frequency adjustment, then frequency precision is improved, but reference signal fetching errors increase due to long packet data counting requirements
Solution Approach 1:
The system uses 4-bit reference data for coarse tuning (partial action) and 20-bit reference data for fine tuning (excessive action). This staged approach achieves high precision without requiring excessively long reference signal counting throughout the entire adjustment process, thereby reducing reference signal fetching errors.
3Reliability
If high frequency timing is used for error counting, then reference signal fetching accuracy is improved, but device complexity and timing requirements increase
Solution Approach 1:
The system uses low-frequency timing signals (e.g., 12 MHz oscillator) combined with multi-bit reference data counting instead of expensive high-frequency timing circuits. This approach achieves the required accuracy using simpler, lower-cost timing components.
4Measurement precision
If long USB packet data counting is used as reference signals, then frequency adjustment accuracy is improved, but lock time and reference signal fetching errors increase
Solution Approach 1:
The reference data counting is segmented into two phases: coarse tuning uses 4-bit reference data for quick initial adjustment, while fine tuning uses 20-bit reference data for precise final adjustment. This segmentation achieves high accuracy without requiring the entire fine-tuning process to wait for long packet data accumulation.
Data Source
AI summary
An adjusting frequency device of built-in oscillator for USB interface and a method thereof are described. It is Auto detect the error of bit-rate between the USB host and the USB device, and produce tiny counting time for clocking the clock error between the USB host and the USB device by a delay lock loop. The clock error after quantification, digitization and operation outputting a quantitative code, then the oscillator adjusts the oscillation frequency according to the quantitative code. Whereby adjusting the oscillation frequency of the USB device and the frequency of the USB host to less than 1% clock error for ensuring the accuracy of data transmission.