Single-Wire Error Detection Circuit for USB Type-C PD Communication Speed
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Solution Overview
Problem
Power Delivery (PD) communication over USB type-C standard faces challenges in increasing communication speed due to time-division data transmission and requires significant time for error detection through Cyclical Redundancy Check (CRC) after demodulation and decoding.
Innovation Solution
An electronic device with an interface module for single-wire communication, an error detection circuit, and a processor that monitors the output of the error detection circuit during packet reception to rapidly detect errors, allowing for immediate retransmission requests and improving communication speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If PD communication uses time-division data transmission over a single communication line, then device compatibility and power delivery functionality are improved, but communication speed deteriorates
Solution Approach 1:
The patent applies preliminary action by performing error detection at the physical layer before demodulation and decoding operations. The error detection circuit continuously monitors the received signal and detects errors in real-time during the packet reception process, rather than waiting until after complete packet processing. This preliminary error detection enables faster identification of transmission issues without requiring full packet decomposition and analysis, thereby improving communication speed while maintaining compatibility with existing PD communication infrastructure
2Measurement precision
If PD communication performs error detection through CRC after demodulation and decoding, then error detection accuracy is improved, but detection time increases
Solution Approach 1:
The patent applies segmentation by dividing the error detection function into two independent components: a physical layer error detection circuit that operates on raw received signals, and the traditional CRC validation that operates on decoded packets. The error detection circuit is segmented from the main packet processing pipeline, allowing it to continuously monitor signals and provide early error warnings independently. This segmentation enables parallel operation of multiple detection mechanisms, reducing overall detection time while maintaining comprehensive error detection accuracy through both methods working together
3Reliability
If PD communication processes packets through complete demodulation and decoding before error detection, then reliable error identification is improved, but overall communication efficiency deteriorates
Solution Approach 1:
The patent implements preliminary action by establishing an error detection circuit at the physical layer that continuously monitors incoming signals before they undergo demodulation and decoding. This circuit performs initial error assessment on raw received data, providing early warning of transmission issues. When errors are detected preliminarily, the system can immediately request retransmission without completing the full packet processing sequence, thereby maintaining reliable error identification while significantly improving communication efficiency by avoiding unnecessary processing of corrupted packets
Solution Approach 2:
The patent applies skipping by enabling the system to bypass complete packet processing when errors are detected by the physical layer error detection circuit. Instead of forcing completion of demodulation and decoding for every received packet, the system can rapidly skip ahead and request retransmission upon early error detection. This rushing through of the error detection phase allows the system to maintain high reliability by still using comprehensive error checking methods, while improving productivity by avoiding time-consuming processing of obviously corrupted packets
Data Source
AI summary
An example electronic device may include an interface module including a communication terminal for single-wire communication, an error detection circuit connected to the communication terminal, and at least one processor operatively coupled to the error detection circuit. The at least one processor monitors an output of the error detection circuit located between the communication terminal and the at least one processor while receiving a packet from an external electronic device when performing single-wire communication with the external electronic device connected through the interface module, and detects whether an error occurs based on a result of the monitoring.